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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] Better scheduling/selection of the LEA instruction"
href="https://bugs.llvm.org/show_bug.cgi?id=32326">32326</a>
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<th>Summary</th>
<td>[X86] Better scheduling/selection of the LEA instruction
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: X86
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>llvm-dev@redking.me.uk
</td>
</tr>
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<th>CC</th>
<td>andrew.v.tischenko@gmail.com, llvm-bugs@lists.llvm.org, spatel+llvm@rotateright.com
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<th>Blocks</th>
<td>32325
</td>
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<p>
<div>
<pre>Some basic forms of the LEA instruction (2 source operands, no scale etc.) can
typically be performed on the cpu's generic ALUs whilst the complex forms (3
source operands, scale + offset etc.) can only be performed on a cpus's AGUs.
We need to better tag the different LEA instructions so that we can
discriminate in the scheduler model and compare them against other memory
address instructions.
We should then be able to improve LEA pattern selection in the machine combiner
(balance ALU/AGU usage, use multi stage LEAs for simple integer multiplies
etc.).</pre>
</div>
</p>
<div id="referenced">
<hr style="border: 1px dashed #969696">
<b>Referenced Bugs:</b>
<ul>
<li>
[<a class="bz_bug_link
bz_status_NEW "
title="NEW - [META][X86] Improve implementation and use of X86 scheduler models"
href="https://bugs.llvm.org/show_bug.cgi?id=32325">Bug 32325</a>] [META][X86] Improve implementation and use of X86 scheduler models
</li>
</ul>
</div>
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