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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - ARM, Hexagon, and MIPS emit return blocks for which MBB.isReturnBlock returns false"
href="https://bugs.llvm.org/show_bug.cgi?id=31960">31960</a>
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<th>Summary</th>
<td>ARM, Hexagon, and MIPS emit return blocks for which MBB.isReturnBlock returns false
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: ARM
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>rnk@google.com
</td>
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<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<pre>Kyle noticed that there are many ways that MachineBasicBlock::isReturnBlock can
return false for blocks that actually contain epilogues. It would be nice if
this predicate could remain accurate after prologue/epilogue insertion, because
it informs machine block placement and other optimizations. This came up during
review here: <a href="https://reviews.llvm.org/D29153">https://reviews.llvm.org/D29153</a>
In particular, the ARM load store optimizer turns tBX_RET pseudo-instrs into
tBX indirect branch instructions, which are not flagged with isReturn. Other
targets (Mips, Hexagon) also seem to have this problem. You can find blocks
ending in indirect branches that aren't returns with this patch:
diff --git a/lib/CodeGen/MachineBlockPlacement.cpp
b/lib/CodeGen/MachineBlockPlacement.cpp
index 8a57f00..2ecd083 100644
--- a/lib/CodeGen/MachineBlockPlacement.cpp
+++ b/lib/CodeGen/MachineBlockPlacement.cpp
@@ -2302,6 +2302,15 @@ bool
MachineBlockPlacement::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
return false;
+ for (auto &MBB : MF) {
+ if (!MBB.isReturnBlock() && MBB.succ_empty() && !MBB.empty() &&
+ MBB.back().isIndirectBranch()) {
+ MBB.dump();
+ llvm_unreachable(
+ "found no-successor indirect branch not flagged as return");
+ }
+ }
+
// Check for single-block functions and skip them.
if (std::next(MF.begin()) == MF.end())
return false;
Here's an example where the ARM load/store optimizer creates this
inconsistency:
$ echo 'define i32 @simpleframe(<6 x i32>* %p) #0 {
entry:
%0 = load <6 x i32>, <6 x i32>* %p, align 16
%1 = extractelement <6 x i32> %0, i32 0
%2 = extractelement <6 x i32> %0, i32 1
%3 = extractelement <6 x i32> %0, i32 2
%4 = extractelement <6 x i32> %0, i32 3
%5 = extractelement <6 x i32> %0, i32 4
%6 = extractelement <6 x i32> %0, i32 5
%add1 = add nsw i32 %1, %2
%add2 = add nsw i32 %add1, %3
%add3 = add nsw i32 %add2, %4
%add4 = add nsw i32 %add3, %5
%add5 = add nsw i32 %add4, %6
ret i32 %add5
}
' | llc -mtriple=thumbv4t-none--eabi
It would be nice to clean this up eventually by adding more duplicate indirect
branch pseudo instructions to carry the isReturn flag.</pre>
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