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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - Halide would like to set the .maxnreg directive per PTX kernel."
href="https://llvm.org/bugs/show_bug.cgi?id=31321">31321</a>
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<th>Summary</th>
<td>Halide would like to set the .maxnreg directive per PTX kernel.
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>Other
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: PTX
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>zalman@google.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<th>Classification</th>
<td>Unclassified
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<p>
<div>
<pre>The PTX backend has the ability to generate certain per kernel (.entry) PTX
directives via metadata annotations. The test for this is in
test/CodeGen/NVPTX/annotations.ll . According to this NVIDIA PTX document:
<a href="http://docs.nvidia.com/cuda/parallel-thread-execution/#performance-tuning-directives">http://docs.nvidia.com/cuda/parallel-thread-execution/#performance-tuning-directives</a>
the .maxnreg value can be set on a per entry basis as well. Halide would like
to exploit this to be able to provide a scheduling directive to control this
value. (See:
<a href="https://github.com/halide/Halide/pull/1667">https://github.com/halide/Halide/pull/1667</a>
where there is a hack to set the maximum number of registers on a per module
basis at load time.)
Plumbing this through involves adding support to
NVPTXAsmPrinter::emitKernelFunctionDirectives .</pre>
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