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    <head>
      <base href="https://llvm.org/bugs/" />
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW --- - Can't fold a reload if spill size doesn't match use size"
   href="https://llvm.org/bugs/show_bug.cgi?id=30832">30832</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>Can't fold a reload if spill size doesn't match use size
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Linux
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: X86
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>mkuper@google.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org
          </td>
        </tr>

        <tr>
          <th>Classification</th>
          <td>Unclassified
          </td>
        </tr></table>
      <p>
        <div>
        <pre>This is something we currently explicitly don't do because targets aren't
required to support it (InlinerSpiller::foldMemoryOperand()).

So for:

target triple = "x86_64-unknown-linux-gnu"

define i32 @foo(i64 %add, i32 %ret) {
entry:
  tail call void asm sideeffect "",
"~{rax},~{rbx},~{rcx},~{rdx},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{dirflag},~{fpsr},~{flags}"()
  %conv3 = zext i32 %ret to i64
  %sub = sub i64 %conv3, %add
  %conv1 = trunc i64 %sub to i32
  ret i32 %conv1
}

we generate:

[...]
    movq    %rdi, -8(%rsp)          # 8-byte Spill
    movq    -8(%rsp), %rax          # 8-byte Reload
    subl    %eax, %esi
[...]

The same also happens for vector registers (spill ymm, reload ymm, use xmm).</pre>
        </div>
      </p>
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