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<base href="https://llvm.org/bugs/" />
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<body><table border="1" cellspacing="0" cellpadding="8">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [avx512bw] fatal error: error in backend: Cannot select: t127: v32i8 = X86ISD::VTRUNC t126"
href="https://llvm.org/bugs/show_bug.cgi?id=30600">30600</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>[avx512bw] fatal error: error in backend: Cannot select: t127: v32i8 = X86ISD::VTRUNC t126
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Linux
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Backend: X86
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>rtrieu@google.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr>
<tr>
<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>$ cat reduce.ii
char *x0;
void x6(int);
void x1(x2) {
char x3, x4;
int x5 = 0;
for (; x5 < x2; x5++)
if (x0)
if (x0[x5] < x3)
x3 = x0[x5];
x4 = x3;
x6(x4);
}
$ clang "-cc1" "-triple" "x86_64-linux-gnu" "-emit-obj" "-target-cpu" "x86-64"
"-target-feature" "+avx512bw" "-O2" "-vectorize-loops" "-x" "c" "reduce.ii"
fatal error: error in backend: Cannot select: t127: v32i8 = X86ISD::VTRUNC t126
t126: v16i32 = vselect t47, t101, t103
t47: v32i1 = and t122, t20
t122: v32i1 = X86ISD::CVT2MASK t121
t121: v32i8 = bitcast t123
t123: v16i16 = X86ISD::VSHLI t119, Constant:i8<7>
t119: v16i16 = bitcast t118
t118: v32i8 = X86ISD::PCMPGT t33, t140
t33: v32i8,ch = CopyFromReg t0, Register:v32i8 %vreg13
t32: v32i8 = Register %vreg13
t140: v32i8 = extract_subvector t139, Constant:i64<0>
t139: v64i8,ch =
masked_load<LD32[%scevgep62](align=1)(tbaa=<0x5864dc8>)> t143:1, t18, t167,
undef:v64i8
t61: i64 = Constant<0>
t90: i8 = Constant<7>
t20: v32i1,ch = CopyFromReg t0, Register:v32i1 %vreg7
t19: v32i1 = Register %vreg7
t101: v16i32 = BUILD_VECTOR Constant:i32<-1>, Constant:i32<-1>,
Constant:i32<-1>, Constant:i32<-1>, Constant:i32<-1>, Constant:i32<-1>,
Constant:i32<-1>, Constant:i32<-1>, Constant:i32<-1>, Constant:i32<-1>,
Constant:i32<-1>, Constant:i32<-1>, Constant:i32<-1>, Constant:i32<-1>,
Constant:i32<-1>, Constant:i32<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t100: i32 = Constant<-1>
t103: v16i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<0>,
Constant:i32<0>, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>,
Constant:i32<0>, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>,
Constant:i32<0>, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>,
Constant:i32<0>, Constant:i32<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
t102: i32 = Constant<0>
In function: x1</pre>
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