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<base href="https://llvm.org/bugs/" />
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<body><table border="1" cellspacing="0" cellpadding="8">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - CFG simplify sink performance regression on AArch64 in libcxx std::map"
href="https://llvm.org/bugs/show_bug.cgi?id=30452">30452</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>CFG simplify sink performance regression on AArch64 in libcxx std::map
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Linux
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Scalar Optimizations
</td>
</tr>
<tr>
<th>Assignee</th>
<td>james.molloy@arm.com
</td>
</tr>
<tr>
<th>Reporter</th>
<td>brzycki@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org, sebpop@gmail.com
</td>
</tr>
<tr>
<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>The following commit causes an extra load inside a loop.
commit 808cdf24ff6941f8a2179abecb5c7e80a758a04a
Author: James Molloy <<a href="mailto:james.molloy@arm.com">james.molloy@arm.com</a>>
Date: Sun Sep 11 09:00:03 2016 +0000
[SimplifyCFG] Be even more conservative in SinkThenElseCodeToEnd
This should *actually* fix PR30244. This cranks up the workaround for
PR30188 so that we never sink loads or stores of allocas.
The idea is that these should be removed by SROA/Mem2Reg, and any movement
of them may well confuse SROA or just cause unwanted code churn. It's not ideal
that the midend should be crippled like this, but that unwanted churn can
really cause significant regressions in important workloads (tsan).
$ cat foo.cpp
#include <map>
int test(unsigned *keys, std::map<int, int> &m_map)
{
int i, last_index, sane=0;
for (i=0, last_index = 0; i<100; i++)
{
auto it = m_map.find(keys[last_index++]);
if (it != m_map.end())
sane += it->second;
}
return sane;
}
$ clang++ foo.cpp -O3 -S -o out.s
--- good.s 2016-09-19 17:25:03.708062780 -0500
+++ bad.s 2016-09-19 17:25:26.584666253 -0500
@@ -6,7 +6,7 @@
_Z4testPjRNSt3__13mapIiiNS0_4lessIiEENS0_9allocatorINS0_4pairIKiiEEEEEE: //
@_Z4testPjRNSt3__13mapIiiNS0_4lessIiEENS0_9allocatorINS0_4pairIKiiEEEEEE
// BB#0: // %entry
ldr x9, [x1, #8]!
- cbz x9, .LBB0_9
+ cbz x9, .LBB0_11
// BB#1: // %for.body.preheader
mov x10, xzr
mov w8, wzr
@@ -14,40 +14,46 @@
// =>This Loop Header: Depth=1
// Child Loop BB0_3 Depth 2
ldr w12, [x0, x10, lsl #2]
+ add x10, x10, #1 // =1
mov x11, x1
mov x13, x9
.LBB0_3: // %while.body.i.i.i
// Parent Loop BB0_2 Depth=1
// => This Inner Loop Header: Depth=2
ldr w14, [x13, #28]
- add x15, x13, #8 // =8
cmp w14, w12
- csel x11, x11, x13, lt
- csel x13, x15, x13, lt
+ b.ge .LBB0_5
+// BB#4: // %if.else.i.i.i
+ // in Loop: Header=BB0_3 Depth=2
+ ldr x13, [x13, #8]
+ cbnz x13, .LBB0_3
+ b .LBB0_6
+.LBB0_5: // %if.then.i.i.i
+ // in Loop: Header=BB0_3 Depth=2
+ mov x11, x13
ldr x13, [x13]
cbnz x13, .LBB0_3</pre>
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