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<base href="https://llvm.org/bugs/" />
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - ARM64 assembler does not set shift bits on add instruction to calculate TLS address"
href="https://llvm.org/bugs/show_bug.cgi?id=30436">30436</a>
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<th>Summary</th>
<td>ARM64 assembler does not set shift bits on add instruction to calculate TLS address
</td>
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<th>Product</th>
<td>new-bugs
</td>
</tr>
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<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>new bugs
</td>
</tr>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>Lei.Liu2@windriver.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
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<th>Classification</th>
<td>Unclassified
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</tr></table>
<p>
<div>
<pre>ARM64 assembler generates invalid code sequence to access TLS variables in
local-exec TLS model. In particular, the add instruction generated to
calculate the higher 12-bit value of TLS offset does not set its shift bit, so
the immediate value is incorrectly added to the lower part of the register.
E.g.
.text
.align 2
.global foo
.type foo, %function
foo:
mrs x0, tpidr_el0
add x0, x0, #:tprel_hi12:ta
add x0, x0, #:tprel_lo12_nc:ta
Assembled with clang --target=arm64.
0000000000000000 <foo>:
0: d53bd040 mrs x0, tpidr_el0
4: 91000000 add x0, x0, #0x0
8: 91000000 add x0, x0, #0x0
Assembled with aarch64-linux-gnu-gcc.
0000000000000000 <foo>:
0: d53bd040 mrs x0, tpidr_el0
4: 91400000 add x0, x0, #0x0, lsl #12
8: 91000000 add x0, x0, #0x0</pre>
</div>
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