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<base href="https://llvm.org/bugs/" />
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - Scheduler disregards aliasing for stack slots resulting in miscompilation"
href="https://llvm.org/bugs/show_bug.cgi?id=30197">30197</a>
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<th>Summary</th>
<td>Scheduler disregards aliasing for stack slots resulting in miscompilation
</td>
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<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Common Code Generator Code
</td>
</tr>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>simon.dardis@imgtec.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
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<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>Created <span class=""><a href="attachment.cgi?id=17183" name="attach_17183" title="Minimal test case.">attachment 17183</a> <a href="attachment.cgi?id=17183&action=edit" title="Minimal test case.">[details]</a></span>
Minimal test case.
The simple attached program is miscompiled when the postRA scheduler is run.
The test case program has function that tail calls another function with the
arguments reordered. Crucially, the arguments that are to be re-ordered are
passed on the stack.
The program below clobbers overwrites one of the passed arguments as the
scheduler does not consider invariant loads of arguments from the stack in the
presence of writes to the argument area of the stack.
Before the PostRA scheduler:
%GP<def> = ADDu %V0, %T9
%AT<def> = LW %SP, 20; mem:LD4[FixedStack-2]
%V0<def> = LW %SP, 16; mem:LD4[FixedStack-1](align=8)
SW %A1<kill>, %SP, 20; mem:Volatile ST4[FixedStack-4]
SW %V0<kill>, %SP, 16; mem:Volatile ST4[FixedStack-3](align=8)
%T9<def> = LW %GP, <ga:@func1>[TF=2]; mem:LD4[GlobalValueCallEntry]
%A1<def> = OR %AT<kill>, %ZERO
TAILCALLREG %T9, <regmask %FP %RA %D10 %D11 %D12 %D13 %D14 %D15 %F20
%F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %S0 %S1 %S2 %S3 %S4 %S5
%S6 %S7>, %AT<imp-def,dead>, %A0<imp-use>, %A1<imp-use>, %A2<imp-use>,
%A3<imp-use>, %GP<imp-use>
After:
%GP<def> = ADDu %V0<kill>, %T9<kill>
%V0<def> = LW %SP, 16; mem:LD4[FixedStack-1](align=8)
** SW %A1<kill>, %SP, 20; mem:Volatile ST4[FixedStack-4]
** %AT<def> = LW %SP, 20; mem:LD4[FixedStack-2]
SW %V0<kill>, %SP, 16; mem:Volatile ST4[FixedStack-3](align=8)
%T9<def> = LW %GP, <ga:@func1>[TF=2]; mem:LD4[GlobalValueCallEntry]
%A1<def> = OR %AT<kill>, %ZERO
TAILCALLREG %T9<kill>, <regmask %FP %RA %D10 %D11 %D12 %D13 %D14 %D15
%F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %S0 %S1 %S2 %S3 %S4
%S5 %S6 %S7>, %AT<imp-def,dead>, %A0<imp-use,kill>, %A1<imp-use,kill>,
%A2<imp-use,kill>, %A3<imp-use,kill>, %GP<imp-use,kill>
The re-ordering of ** instructions clobbers 20(sp) too early.
Removing the check isInvariantLoad in ScheduleDAGInstrs::buildSchedGraph
produces the correct code. I'm not sure if that's the correct solution.</pre>
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