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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [x86, SSE] failed to simplify vector select with zero constant to 'andn'"
href="https://llvm.org/bugs/show_bug.cgi?id=28925">28925</a>
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<th>Summary</th>
<td>[x86, SSE] failed to simplify vector select with zero constant to 'andn'
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>All
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
</tr>
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<th>Component</th>
<td>Backend: X86
</td>
</tr>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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</tr>
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<th>Reporter</th>
<td>spatel+llvm@rotateright.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
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<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
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<pre>Follow-up from <a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [x86, SSE] failed to simplify vector select with zero constant to 'and'"
href="show_bug.cgi?id=28895">bug 28895</a> / <a href="https://reviews.llvm.org/D23337">https://reviews.llvm.org/D23337</a> :
define <4 x i32> @test1(<4 x i1> %cond, <4 x i32> %x) {
%r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x
ret <4 x i32> %r
}
Double-check the truth tables and x86 operand order, but I think this could be
'pandn' rather than 'blendv':
$ ./llc -o - -mattr=avx sel.ll
vpslld $31, %xmm0, %xmm0
vxorps %xmm2, %xmm2, %xmm2
vblendvps %xmm0, %xmm2, %xmm1, %xmm0
retq
-----------------------------------------------------------------------------
vpslld $31, %xmm0, %xmm0
vpsrad $31, %xmm0, %xmm0
vpandn %xmm1, %xmm0, %xmm0 ; ~%cond & %x
-----------------------------------------------------------------------------
In the normal case (?), we'd expect the compare instruction that produces the
condition operand to be in the function:
define <4 x i32> @test2(<4 x float> %a, <4 x float> %b, <4 x i32> %x) {
%cond = fcmp oeq <4 x float> %a, %b
%r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x
ret <4 x i32> %r
}
Currently, we handle this pattern by inverting the condition rather than using
'andn':
vcmpneqps %xmm0, %xmm1, %xmm0 ; fcmp oeq -> fcmp une
vandps %xmm2, %xmm0, %xmm0
retq
This is done in "combineVSelectWithAllOnesOrZeros()".</pre>
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