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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [X86] AMD Jaguar scheduler doesn't correctly model 256-bit AVX instructions"
href="https://llvm.org/bugs/show_bug.cgi?id=28573">28573</a>
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<th>Summary</th>
<td>[X86] AMD Jaguar scheduler doesn't correctly model 256-bit AVX instructions
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>llvm-dev@redking.me.uk
</td>
</tr>
<tr>
<th>CC</th>
<td>chisophugis@gmail.com, filcab@gmail.com, llvm-bugs@lists.llvm.org, simon.f.whittaker@gmail.com, spatel+llvm@rotateright.com
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<th>Classification</th>
<td>Unclassified
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<p>
<div>
<pre>All current AMD CPUs capable of AVX 'double pump' 256-bit vector operations
through 128-bit vector ALUs.
On Jaguar this means while the latency is typically (but not always) the same
for a xmm and ymm variants, the throughput is half what is predicted by the
scheduler/cost-models. This needs to be accounted for.</pre>
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</p>
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