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<body><span class="vcard"><a class="email" href="mailto:llvm-dev@redking.me.uk" title="Simon Pilgrim <llvm-dev@redking.me.uk>"> <span class="fn">Simon Pilgrim</span></a>
</span> changed
<a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - min/max vector instructions not selected for shorts (16-bit integers)"
href="https://llvm.org/bugs/show_bug.cgi?id=17822">bug 17822</a>
<br>
<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>What</th>
<th>Removed</th>
<th>Added</th>
</tr>
<tr>
<td style="text-align:right;">Status</td>
<td>NEW
</td>
<td>RESOLVED
</td>
</tr>
<tr>
<td style="text-align:right;">CC</td>
<td>
</td>
<td>llvm-dev@redking.me.uk
</td>
</tr>
<tr>
<td style="text-align:right;">Resolution</td>
<td>---
</td>
<td>FIXED
</td>
</tr></table>
<p>
<div>
<b><a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - min/max vector instructions not selected for shorts (16-bit integers)"
href="https://llvm.org/bugs/show_bug.cgi?id=17822#c4">Comment # 4</a>
on <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - min/max vector instructions not selected for shorts (16-bit integers)"
href="https://llvm.org/bugs/show_bug.cgi?id=17822">bug 17822</a>
from <span class="vcard"><a class="email" href="mailto:llvm-dev@redking.me.uk" title="Simon Pilgrim <llvm-dev@redking.me.uk>"> <span class="fn">Simon Pilgrim</span></a>
</span></b>
<pre>Resolving this - general SMIN/SMAX/UMIN/UMAX support has been available on X86
since D9746/D10947. The TargetTransformInfo still doesn't model these but it
doesn't appear to be an issue.
__Z3maxPtS_: ## @_Z3maxPtS_
.cfi_startproc
## BB#0: ## %entry
xorl %eax, %eax
.p2align 4, 0x90
LBB0_1: ## %vector.body
## =>This Inner Loop Header: Depth=1
vmovdqu (%rdi,%rax,2), %xmm0
vmovdqu 16(%rsi,%rax,2), %xmm1
vpmaxuw 16(%rdi,%rax,2), %xmm1, %xmm1
vpmaxuw (%rsi,%rax,2), %xmm0, %xmm0
vmovdqu %xmm1, 16(%rdi,%rax,2)
vmovdqu %xmm0, (%rdi,%rax,2)
vmovdqu 48(%rdi,%rax,2), %xmm0
vmovdqu 32(%rdi,%rax,2), %xmm1
vpmaxuw 32(%rsi,%rax,2), %xmm1, %xmm1
vpmaxuw 48(%rsi,%rax,2), %xmm0, %xmm0
vmovdqu %xmm0, 48(%rdi,%rax,2)
vmovdqu %xmm1, 32(%rdi,%rax,2)
vmovdqu 80(%rdi,%rax,2), %xmm0
vmovdqu 64(%rdi,%rax,2), %xmm1
vpmaxuw 64(%rsi,%rax,2), %xmm1, %xmm1
vpmaxuw 80(%rsi,%rax,2), %xmm0, %xmm0
vmovdqu %xmm0, 80(%rdi,%rax,2)
vmovdqu %xmm1, 64(%rdi,%rax,2)
vmovdqu 112(%rdi,%rax,2), %xmm0
vmovdqu 96(%rdi,%rax,2), %xmm1
vpmaxuw 96(%rsi,%rax,2), %xmm1, %xmm1
vpmaxuw 112(%rsi,%rax,2), %xmm0, %xmm0
vmovdqu %xmm0, 112(%rdi,%rax,2)
vmovdqu %xmm1, 96(%rdi,%rax,2)
addq $64, %rax
cmpq $1024, %rax ## imm = 0x400
jne LBB0_1
## BB#2: ## %for.cond.cleanup
retq</pre>
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