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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [AArch64] Add paired loads/stores to getMemOpBaseRegImmOfsWidth()"
href="https://llvm.org/bugs/show_bug.cgi?id=26358">26358</a>
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<th>Summary</th>
<td>[AArch64] Add paired loads/stores to getMemOpBaseRegImmOfsWidth()
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: AArch64
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<th>Assignee</th>
<td>mcrosier@codeaurora.org
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<th>Reporter</th>
<td>mcrosier@codeaurora.org
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<th>CC</th>
<td>bmakam@codeaurora.org, gberry@codeaurora.org, haicheng@codeaurora.org, junbuml@codeaurora.org, llvm-bugs@lists.llvm.org, mssimpso@codeaurora.org
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<th>Classification</th>
<td>Unclassified
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<p>
<div>
<pre>The target specific hook areMemAccessesTriviallyDisjoint() is used by the MI
scheduler to determine if two memory access are disjoint (i.e., don't alias).
The helper function getMemOpBaseRegImmOfsWidth() should include all of the
paired instructions (e.g., STPSi, LDPSi, etc.), so the scheduler has more
flexibility when scheduling.
First <a href="http://reviews.llvm.org/D8705">http://reviews.llvm.org/D8705</a> needs to land, so the scheduler better
handles instructions with multiple MMOs. Then mergePairedInsns() in the
AArch64 load store optimizer needs to be fixed so that the pair instructions
include their MMOs. Once complete then paired instructions can be added to the
getMemOpBaseRegImmOfsWidth() function.</pre>
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