<html>
    <head>
      <base href="https://llvm.org/bugs/" />
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW --- - AArch64 atomic operations disrupted by fast-regalloc"
   href="https://llvm.org/bugs/show_bug.cgi?id=25526">25526</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>AArch64 atomic operations disrupted by fast-regalloc
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: AArch64
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>t.p.northover@gmail.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org
          </td>
        </tr>

        <tr>
          <th>Classification</th>
          <td>Unclassified
          </td>
        </tr></table>
      <p>
        <div>
        <pre>When compiling this at -O0:

    define {i64, i1} @foo(i64* %addr, i64 %desired, i64 %new) {
      %old = cmpxchg i64* %addr, i64 %desired, i64 %new seq_cst seq_cst
      ret {i64, i1} %old
    }

Fast-regalloc seems to insert many spills between the ldaxr and the stlxr. If
these are on the same cache-line as %addr (in practice) then they can reset the
monitor causing the operation to fail.

ARM is almost certainly affected too. But both only at -O0.

I'm still not sure what to do about this one. Some obvious options are:

1. Go back to lots of pseudo-instructions for various different uses. Extremely
nasty, we worked very hard to get rid of those for better codegen.
2. Disable fast-regalloc in all cases. Probably bad for debug quality, so I
doubt this is viable.
3. Emit libcalls at -O0. I'm not sure all platforms support these though, we'd
have to make sure they're available.</pre>
        </div>
      </p>
      <hr>
      <span>You are receiving this mail because:</span>
      
      <ul>
          <li>You are on the CC list for the bug.</li>
      </ul>
    </body>
</html>