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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [x86] avoid big bad immediates in the instruction stream, part 1: use SIB addressing"
href="https://llvm.org/bugs/show_bug.cgi?id=24447">24447</a>
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<th>Summary</th>
<td>[x86] avoid big bad immediates in the instruction stream, part 1: use SIB addressing
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>spatel+llvm@rotateright.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<th>Classification</th>
<td>Unclassified
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<p>
<div>
<pre>This report is based on the post-commit thread for r244601:
<a href="http://reviews.llvm.org/rL244601">http://reviews.llvm.org/rL244601</a>
<a href="http://reviews.llvm.org/D11363">http://reviews.llvm.org/D11363</a>
Sean Silva observed sequences of 11-byte (!) instructions:
20b7f: 48 c7 80 78 01 00 00 00 00 00 00 movq $0, 376(%rax)
20b8a: 48 c7 80 80 01 00 00 00 00 00 00 movq $0, 384(%rax)
20b95: 48 c7 80 88 01 00 00 00 00 00 00 movq $0, 392(%rax)
...
One way to reduce this bloat - use SIB addressing to reduce the cost of the
32-bit address offsets:
movl $376, %ebx [bb 78 01 00 00]
movq $0, (%rax,%rbx) [48 c7 04 18 00 00 00 00]
movq $0, 8(%rax,%rbx) [48 c7 44 18 08 00 00 00 00]
movq $0, 16(%rax,%rbx) [48 c7 44 18 10 00 00 00 00]
...that's 31 bytes instead of 33.
The size savings formula for enabling this optimization is:
+5 bytes for the extra movl
-4 bytes for the first instruction not needing an offset
+1 byte for the first SIB
-3 bytes for each additional instruction that can now use an 8-bit offset
rather than 32-bit
+1 byte for each instruction's SIB byte
So if (5 - 4 + 1 + (N - 1) * (-3 + 1)) < 0, do it:
2 + -2N + 2 < 0
N > 2
We can do this to save size anytime we have at least 3 instructions that can
use 8-bit offsets from the same 32-bit base address.
The hope is that this transform also improves *performance* for all recent
chips despite increasing the official instruction count. The key to make that
generalization is that storing immediates is actually more expensive than
storing a register.
Immediate stores may be implemented micro-architecturally using 2 uops rather
than 1 uop (see AMD SOG for Jaguar), and/or repeated 32-bit immediates cause a
uop cache to lose effectiveness (see Intel Optimization Manual rules 38 and
39).</pre>
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