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<base href="https://llvm.org/bugs/" />
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<body><table border="1" cellspacing="0" cellpadding="8">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW " title="NEW --- - Sibling loops confuse spill placement" href="https://urldefense.proofpoint.com/v2/url?u=https-3A__llvm.org_bugs_show-5Fbug.cgi-3Fid-3D23743&d=AwMBaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=pF93YEPyB-J_PERP4DUZOJDzFVX5ZQ57vQk33wu0vio&m=v-bjmL7W8dWTGeLD-2Z85dGoSfhrnmDI36bzJzIcTAo&s=gnrKBCHYWgVjcjet52U2rytcd35QjnVFZK0E23d8GzY&e=">23743</a>
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<th>Summary</th>
<td>Sibling loops confuse spill placement
</td>
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<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
</tr>
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<th>Component</th>
<td>Register Allocator
</td>
</tr>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>james.molloy@arm.com
</td>
</tr>
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<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
</td>
</tr>
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<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>Created <span class=""><a href="attachment.cgi?id=14426" name="attach_14426" title="Testcase">attachment 14426</a> <a href="attachment.cgi?id=14426&action=edit" title="Testcase">[details]</a></span>
Testcase
In the attached testcase there is one loop with two child loops. The two child
loops are siblings to each other.
A reloaded is inserted in the second sibling loop, instead of a different
register being spilled outside the second loop.
The register being spilled is %vreg7:
selectOrSplit rGPR:%vreg45 [576r,656B:0)[656B,976r:1)[976r,1104B:2) 0@576r
1@656B-phi 2@976r w=2.185477e+05
%R10 is available at cost 1
Only trying the first 10 regs.
should evict: %vreg23 [160r,1184B:0) 0@160r w= 4.682460e+04
should evict: %vreg1 [80r,1184B:0) 0@80r w= 2.164171e+04
should evict: %vreg8 [560r,1104B:0) 0@560r w= 2.003648e+04
should evict: %vreg7 [496r,1104B:0) 0@496r w= 1.771947e+04
evicting %R6 interference: Cascade 4
unassigning %vreg7 from %R6: R6
assigning %vreg45 to %R6: R6 [576r,656B:0)[656B,976r:1)[976r,1104B:2) 0@576r
1@656B-phi 2@976r
queuing new interval: %vreg7 [496r,1104B:0) 0@496r
%vreg7 has the lowest spill cost because it is within an if/else inside the
second loop. However, spilling %vreg23 or %vreg1 would not be as costly as
%vreg7 because both of those registers are live-through the second loop (they
are only used in the first loop).
It appears the spill placement algorithm is aware of loop nest depth (implied
by block frequency) but unaware of loop hierarchy.
Compile with: llc -O3 test.ll and note:
.LBB0_5: @ %bb21
@ Parent Loop BB0_2 Depth=1
@ => This Inner Loop Header: Depth=2
sub.w r8, r7, #2
cmp r8, r4
bhi .LBB0_7
@ BB#6: @ %bb27
@ in Loop: Header=BB0_5 Depth=2
ldrb.w r5, [r9, r7]
lsl.w r2, lr, r11
eors r2, r5
ldr r5, [sp, #8] @ 4-byte Reload ***NAUGHTY***
and.w lr, r2, r5</pre>
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