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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - support AARCH32 cp15 register access by mrs/msr and name"
href="http://llvm.org/bugs/show_bug.cgi?id=22794">22794</a>
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<th>Summary</th>
<td>support AARCH32 cp15 register access by mrs/msr and name
</td>
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<th>Product</th>
<td>clang
</td>
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<th>Version</th>
<td>3.6
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>-New Bugs
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<th>Assignee</th>
<td>unassignedclangbugs@nondot.org
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<th>Reporter</th>
<td>axelheider@gmx.de
</td>
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<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
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<th>Classification</th>
<td>Unclassified
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<p>
<div>
<pre>Support ARMv7/AARCH32 cp15 register access via mrs/msr and names instead of the
cryptic mrc/mcr would be nice. ARM has added support in ARMCC V5 added support
for it:
asm ("mrs %0, MPIDR" : "=r" (val));
so for Clang still this (cryptic) must be used:
asm ("mrc p15,0,%0,c0,c0,5;" : "=r" (val));
When targeting AARCH64 the names work nicely:
asm ("mrs %0, MPIDR_EL1"=r" (val));
At some point, native supporting this for 64-bit registers via a similar
mechnism would also be a nice thing. See
<a href="http://community.arm.com/groups/tools/blog/2014/10/16/msrrmrrs--a-asm-macro-for-64-bit-named-registers">http://community.arm.com/groups/tools/blog/2014/10/16/msrrmrrs--a-asm-macro-for-64-bit-named-registers</a>
So the cryptic
asm ("mrrc p15,0,%0,%1,c7":"=r"(val0),"=r"(val1));
can be used as this pseudo instruction:
asm ("mrrs %0,%1,PAR":"=r"(val0),"=r"(val1));</pre>
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