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<base href="http://llvm.org/bugs/" />
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<body><table border="1" cellspacing="0" cellpadding="8">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [X86][AVX] consecutive 2 x 128 bit loads are not always merged into a single 256 bit load"
href="http://llvm.org/bugs/show_bug.cgi?id=22329">22329</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>[X86][AVX] consecutive 2 x 128 bit loads are not always merged into a single 256 bit load
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>All
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Backend: X86
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>spatel+llvm@rotateright.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
</td>
</tr>
<tr>
<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>The fix for <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [X86][AVX] separate 2x128bit loads are not being merged into a single 256bit load."
href="show_bug.cgi?id=21709">bug 21709</a> is incomplete; only the first 2 loads got merged:
$ cat load32.ll
declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>,
i8)
define <8 x float> @foo(<4 x float>* %x) {
%idx1 = getelementptr inbounds <4 x float>* %x, i64 1
%idx2 = getelementptr inbounds <4 x float>* %x, i64 2
%idx3 = getelementptr inbounds <4 x float>* %x, i64 3
%idx4 = getelementptr inbounds <4 x float>* %x, i64 4
%idx5 = getelementptr inbounds <4 x float>* %x, i64 5
%a0 = load <4 x float>* %x, align 16
%a1 = load <4 x float>* %idx1, align 16
%b0 = load <4 x float>* %idx2, align 16
%b1 = load <4 x float>* %idx3, align 16
%c0 = load <4 x float>* %idx4, align 16
%c1 = load <4 x float>* %idx5, align 16
%shuffle1 = shufflevector <4 x float> %a0, <4 x float> undef, <8 x i32> <i32
0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%shuffle2 = shufflevector <4 x float> %b0, <4 x float> undef, <8 x i32> <i32
0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%shuffle3 = shufflevector <4 x float> %c0, <4 x float> undef, <8 x i32> <i32
0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%a = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>
%shuffle1, <4 x float> %a1, i8 1)
%b = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>
%shuffle2, <4 x float> %b1, i8 1)
%c = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>
%shuffle3, <4 x float> %c1, i8 1)
%add1 = fadd <8 x float> %a, %b
%add2 = fadd <8 x float> %add1, %c
ret <8 x float> %add2
}
$ ./llc -mattr=+avx load32.ll -o -
...
vmovaps 32(%rdi), %xmm0
vmovaps 64(%rdi), %xmm1
vmovups (%rdi), %ymm2
vinsertf128 $1, 48(%rdi), %ymm0, %ymm0
vinsertf128 $1, 80(%rdi), %ymm1, %ymm1
vaddps %ymm0, %ymm2, %ymm0
vaddps %ymm1, %ymm0, %ymm0
retq</pre>
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