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<base href="http://llvm.org/bugs/" />
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - Changing the scheduling would help removing a copy and improve the throughput by 7%"
href="http://llvm.org/bugs/show_bug.cgi?id=21792">21792</a>
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<th>Summary</th>
<td>Changing the scheduling would help removing a copy and improve the throughput by 7%
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>All
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Backend: X86
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>qcolombet@apple.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
</td>
</tr>
<tr>
<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>Created <span class=""><a href="attachment.cgi?id=13445" name="attach_13445" title="bitcode to reproduce">attachment 13445</a> <a href="attachment.cgi?id=13445&action=edit" title="bitcode to reproduce">[details]</a></span>
bitcode to reproduce
In the attached bitcode, we generate the sequence of instructions with a
useless move:
[…]
pshufd $78, %xmm0, %xmm1 ## xmm1 = xmm0[2,3,0,1]
movd %xmm1, %rcx
movd %xmm0, %rdx
movq %rdx, %rax ## <— this move can be removed.
sarq $32, %rax
movslq %edx, %r8
By slightly changing the scheduling, we would be able to get rid of that move:
pshufd $78, %xmm0, %xmm1 ## xmm1 = xmm0[2,3,0,1]
movd %xmm1, %rcx
movd %xmm0, %rdx
movq %rdx, %rax ## <— this move can be removed.
movslq %edx, %r8 ## <— move the sign extension before the
shift.
sarq $32, %rax
Now, the move can be removed:
pshufd $78, %xmm0, %xmm1 ## xmm1 = xmm0[2,3,0,1]
movd %xmm1, %rcx
movd %xmm0, %rax ## rdx becomes rax (the previous move is
coalesce able).
movslq %eax, %r8 ## update the sign extension.
sarq $32, %rax
According to IACA, the old sequence has a throughput of 4.7 cycles, whereas the
new one has a throughput of 4.4 cycles.
The related benchmark improves by 2% because of this change.
** To Reproduce **
llc -mtriple=x86_64-apple-macosx < new.ll
Note: The machine IR looks like this:
%vreg2<def> = PSHUFDri %vreg1, 78; VR128:%vreg2,%vreg1
%vreg3<def> = MOVPQIto64rr %vreg2<kill>; GR64:%vreg3 VR128:%vreg2
%vreg4<def> = MOVPQIto64rr %vreg1; GR64:%vreg4 VR128:%vreg1
%vreg5<def,tied1> = SAR64ri %vreg4<tied0>, 32, %EFLAGS<imp-def,dead>;
GR64_NOSP:%vreg5 GR64:%vreg4
%vreg6<def> = COPY %vreg4:sub_32bit; GR32:%vreg6 GR64:%vreg4
%vreg7<def> = MOVSX64rr32 %vreg6<kill>; GR64_NOSP:%vreg7 GR32:%vreg6
And to get rid of the interference that prevents the copy to be coalesced, we
should schedule it like this:
%vreg2<def> = PSHUFDri %vreg1, 78; VR128:%vreg2,%vreg1
%vreg3<def> = MOVPQIto64rr %vreg2<kill>; GR64:%vreg3 VR128:%vreg2
%vreg4<def> = MOVPQIto64rr %vreg1; GR64:%vreg4 VR128:%vreg1
%vreg6<def> = COPY %vreg4:sub_32bit; GR32:%vreg6 GR64:%vreg4
%vreg7<def> = MOVSX64rr32 %vreg6<kill>; GR64_NOSP:%vreg7 GR32:%vreg6
%vreg5<def,tied1> = SAR64ri %vreg4<tied0>, 32, %EFLAGS<imp-def,dead>;
GR64_NOSP:%vreg5 GR64:%vreg4
I.e., moving vreg5 after vreg7.
The fixing may need to be done in the machine scheduler, but starting with X86
backend.</pre>
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