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<base href="http://llvm.org/bugs/" />
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<body><table border="1" cellspacing="0" cellpadding="8">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [aarch64] miscompile llvm.ctpop.i32"
href="http://llvm.org/bugs/show_bug.cgi?id=21675">21675</a>
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<th>Summary</th>
<td>[aarch64] miscompile llvm.ctpop.i32
</td>
</tr>
<tr>
<th>Product</th>
<td>tools
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Windows NT
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
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<th>Component</th>
<td>llc
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>cole945@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
</td>
</tr>
<tr>
<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>This code loads v2i32 to count 1-bits in the 1st element.
The result is wrong, because the 2nd element is also being counted.
The original case counts both elements, this is just a reduced
case in order to reproduce the bug.
Bitcode for reproducing the case
-- >8 -- >8 -- >8 -- >8 -- >8 -- >8 -- >8 -- >8 -- >8 --
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnueabihf"
declare i32 @llvm.ctpop.i32(i32) #1
define i32 @cnt2(<2 x i32> addrspace(1)* %src) {
%1 = getelementptr inbounds <2 x i32> addrspace(1)* %src, i64 0
%2 = load <2 x i32> addrspace(1)* %1, align 8
%3 = extractelement <2 x i32> %2, i64 0
%4 = tail call i32 @llvm.ctpop.i32(i32 %3) #2
ret i32 %4
}
-- 8< -- 8< -- 8< -- 8< -- 8< -- 8< -- 8< -- 8< -- 8< --
Actual result:
ldr d0, [x0]
cnt v0.8b, v0.8b
uaddlv h0, v0.8b
fmov w0, s0
ret
Expected result:
ldr d0, [x0]
mov s0, v0.s[0] <--
cnt v0.8b, v0.8b
uaddlv h0, v0.8b
fmov w0, s0
ret
Without the 'mov' to clear upper 32-bit,
the 2nd element is being counted.
I think this is a bug of 'LowerCTPOP'.
Insert-subreg doesn't enforces the semantic of zero-extend.
A explicit zero-extend must be used instead.
Otherwise, the COPY (insert-subreg) will be eliminated by
register-coalescing pass.
-- >8 -- >8 -- >8 -- >8 -- >8 -- >8 -- >8 -- >8 -- >8 --
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp
b/lib/Target/AArch64/AArch64ISelLowering.cpp
index 1d74f6e..69cde10 100644
--- a/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3116,18 +3116,13 @@ SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op,
SelectionDAG &DAG) const {
SDValue Val = Op.getOperand(0);
SDLoc DL(Op);
EVT VT = Op.getValueType();
- SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
- SDValue VecVal;
if (VT == MVT::i32) {
- VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
- VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
- VecVal);
- } else {
- VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
+ Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
}
+ Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
- SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
+ SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
SDValue UaddLV = DAG.getNode(
ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
--
-- 8< -- 8< -- 8< -- 8< -- 8< -- 8< -- 8< -- 8< -- 8< --</pre>
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