<html>
<head>
<base href="http://llvm.org/bugs/" />
</head>
<body><table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - Assertion failed: (Op.getValueType() == MVT::f16 && "Inconsistent bitcast? Only 16-bit types should be i16 or f16"), function ReplaceBITCASTResults"
href="http://llvm.org/bugs/show_bug.cgi?id=21549">21549</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>Assertion failed: (Op.getValueType() == MVT::f16 && "Inconsistent bitcast? Only 16-bit types should be i16 or f16"), function ReplaceBITCASTResults
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>All
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Backend: AArch64
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>grosbach@apple.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
</td>
</tr>
<tr>
<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>Created <span class=""><a href="attachment.cgi?id=13327" name="attach_13327" title="llvm-stress testcase">attachment 13327</a> <a href="attachment.cgi?id=13327&action=edit" title="llvm-stress testcase">[details]</a></span>
llvm-stress testcase
Vector types that end up 16-bits in size break that assertion.
(lldb) p N->dumpr()
0x104ccdc08: i16 = bitcast [ORD=3] [ID=0] 0x104ccdb00
0x104ccdb00: v16i1 = vector_shuffle<0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0> [ORD=3]
[ID=-3] 0x104ccd8f0, 0x10404af18: v16i1 = undef [ID=-3]
Context is:
static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) {
if (N->getValueType(0) != MVT::i16)
return;
SDLoc DL(N);
SDValue Op = N->getOperand(0);
assert(Op.getValueType() == MVT::f16 &&
"Inconsistent bitcast? Only 16-bit types should be i16 or f16");
Op = SDValue(
DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
DAG.getUNDEF(MVT::i32), Op,
DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
0);
Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
}
Using an insert_subreg w/ a vector type (especially a non-legal one like v16i1)
is likely to go extremely poorly. Somewhere earlier we've done some custom
lowering that results in this bitcast. Either that code shouldn't be doing that
at all (likely) or this code needs to know how to deal with vectors that end up
16 bits in size. One could probably construct a testcase from v2i8 here as well
to avoid the oddness of vectors of i1.</pre>
</div>
</p>
<hr>
<span>You are receiving this mail because:</span>
<ul>
<li>You are on the CC list for the bug.</li>
</ul>
</body>
</html>