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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [ARM] Allow selection of the SMULW[BT] and SMLAW[BT] instructions"
href="http://llvm.org/bugs/show_bug.cgi?id=21297">21297</a>
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<th>Summary</th>
<td>[ARM] Allow selection of the SMULW[BT] and SMLAW[BT] instructions
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>All
</td>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: ARM
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>oliver.stannard@arm.com
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<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
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<th>Classification</th>
<td>Unclassified
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<p>
<div>
<pre>Our current instruction selection for the SMULW[BT] and SMLAW[BT] instructions
is incorrect (<a class="bz_bug_link
bz_status_NEW "
title="NEW --- - ARM code emitter misoptimization with 16-bit multiplication"
href="show_bug.cgi?id=19396">http://llvm.org/bugs/show_bug.cgi?id=19396</a>), and I have a patch
up for review to remove the incorrect selection patterns
(<a href="http://reviews.llvm.org/D5824">http://reviews.llvm.org/D5824</a>).
However, it should be possible to use these instructions from C code, for
example:
int smulwb(int a, short b) {
return ((long long)a * (long long)b) >> 16;
}
This involves a 64-bit multiply on a 32-bit target, which is an isel DAG node
with two results, so it is not possible to write a pattern to select this. This
would require C++ code to perform the match.</pre>
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