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<base href="http://llvm.org/bugs/" />
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - invalid instruction selection (mule is not permitted within an IT block)"
href="http://llvm.org/bugs/show_bug.cgi?id=20555">20555</a>
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<th>Summary</th>
<td>invalid instruction selection (mule is not permitted within an IT block)
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>All
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>normal
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: ARM
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>compnerd@compnerd.org
</td>
</tr>
<tr>
<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
</td>
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<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>An invalid instruction is selected for the following function:
int function(int i, int j) {
if (i == j)
i = i * j;
return i;
}
The equivalent IR for this:
define arm_aapcs_vfpcc i32 @function(i32 %i, i32 %j) {
entry:
%cmp = icmp eq i32 %i, %j
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
%mul = mul nsw i32 %i, %i
br label %if.end
if.end: ; preds = %if.then, %entry
%i.addr.0 = phi i32 [ %mul, %if.then ], [ %i, %entry ]
ret i32 %i.addr.0
}
Using llc -mtriple thumbv7-eabi -arm-restrict-it -filetype asm -o - %s
generates the following:
function:
cmp r0, r1
it eq
mulseq r0, r0, r0
bx lr
While the logic is correct, the problem is the mulseq which is in an IT block.
The ARM Architecture Reference Manual states:
In the Thumb instruction set, S can be specified only if both <Rn> and <Rm> are
R0-R7 and the instruction is outside an IT block.
This occurs as a result of If Convert + Thumb2SizeReduction. Disabling the
Triangle False (-disable-ifcvt-triangle-false) conversion prevents this from
occurring. It may be the if conversion is changing the liveness state of CPSR.</pre>
</div>
</p>
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