<html>
    <head>
      <base href="http://llvm.org/bugs/" />
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW --- - Oversight in commit r183693"
   href="http://llvm.org/bugs/show_bug.cgi?id=20016">20016</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>Oversight in commit r183693
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>new-bugs
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Linux
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>new bugs
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>hjl.tools@gmail.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvmbugs@cs.uiuc.edu
          </td>
        </tr>

        <tr>
          <th>Classification</th>
          <td>Unclassified
          </td>
        </tr></table>
      <p>
        <div>
        <pre>X86DAGToDAGISel::SelectLEA64_32Addr in commit r183693 has

+    Base = CurDAG->getRegister(0, MVT::i64);
+  else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(N))
{
                                                                           ^
Shouldn't `N' be `Base' here?

+    // Base could already be %rip, particularly in the x32 ABI.

X86InstrInfo::classifyLEAReg has

+    // Virtual register of the wrong class, we have to create a temporary
64-bit
+    // vreg to feed into the LEA.
+    NewSrc = MF.getRegInfo().createVirtualRegister(RC);
+    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
+            get(TargetOpcode::COPY))
+      .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
+        .addOperand(Src);

It doesn't check if `Src' is a 32-bit vreg.  Should it be

if (MF.getRegInfo().getRegClass(SrcReg)->getSize() == 8)
  Do TargetOpcode::COPY
else
  Do TargetOpcode::SUBREG_TO_REG

A testcase:

[hjl@gnu-6 stack-1]$ cat x32-lea-1.ll
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -O2 | FileCheck %s

define void @bar(i32 %x, i32 %d) nounwind uwtable {
entry:
  %a = alloca [8 x i32], align 16
  %cmp = icmp slt i32 %d, 8
  br i1 %cmp, label %if.then, label %if.end

if.then:                                          ; preds = %entry
  %arraydecay = getelementptr inbounds [8 x i32]* %a, i32 0, i32 0
; CHECK: leal    (%rsp), %edi
  call void @foo(i32* %arraydecay) nounwind
  br label %while.cond

while.cond:                                       ; preds = %while.cond,
%if.then
  %d.addr.0 = phi i32 [ %d, %if.then ], [ %inc, %while.cond ]
  %arrayidx = getelementptr inbounds [8 x i32]* %a, i32 0, i32 %d.addr.0
; CHECK: leal    (%rsp,%r{{[^,]*}},4), %eax
  %0 = load i32* %arrayidx, align 4, !tbaa !0
  %cmp1 = icmp eq i32 %0, 0
  %inc = add nsw i32 %d.addr.0, 1
; CHECK: leal    4(%r{{[^,]*}}), %e{{[^,]*}}
  br i1 %cmp1, label %while.end, label %while.cond

while.end:                                        ; preds = %while.cond
  store i32 %x, i32* %arrayidx, align 4, !tbaa !0
; CHECK: leal    (%rsp), %edi
  call void @foo(i32* %arraydecay) nounwind
  br label %if.end

if.end:                                           ; preds = %while.end, %entry
  ret void
}

declare void @foo(i32*)

!0 = metadata !{metadata !"int", metadata !1}
!1 = metadata !{metadata !"omnipotent char", metadata !2}
!2 = metadata !{metadata !"Simple C/C++ TBAA"}
[hjl@gnu-6 stack-1]$ ./llc < x32-lea-1.ll -mtriple=x86_64-linux-gnux32 -O2
    .text
    .file    "<stdin>"
llc: /export/import/git/llvm/include/llvm/CodeGen/MachineOperand.h:265:
unsigned int llvm::MachineOperand::getReg() const: Assertion `isReg() && "This
is not a register operand!"' failed.
0  llc             0x0000000001b009df llvm::sys::PrintStackTrace(_IO_FILE*) +
38
1  llc             0x0000000001b00c5c
2  llc             0x0000000001b0060a
3  libpthread.so.0 0x0000003047c0f770
4  libc.so.6       0x0000003047435b89 gsignal + 57
5  libc.so.6       0x0000003047437298 abort + 328
6  libc.so.6       0x000000304742eae6
7  libc.so.6       0x000000304742eb92
8  llc             0x0000000000a61ffa
9  llc             0x000000000166793c
10 llc             0x0000000001668a7e
11 llc             0x000000000166c874
12 llc             0x000000000153c1d1
llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 95
13 llc             0x0000000001a79ef8
llvm::FPPassManager::runOnFunction(llvm::Function&) + 290
14 llc             0x0000000001a7a068
llvm::FPPassManager::runOnModule(llvm::Module&) + 84
15 llc             0x0000000001a7a3bc
16 llc             0x0000000001a7aa66
llvm::legacy::PassManagerImpl::run(llvm::Module&) + 244
17 llc             0x0000000001a7ac85
llvm::legacy::PassManager::run(llvm::Module&) + 39
18 llc             0x0000000000a147d8
19 llc             0x0000000000a13aa1 main + 237
20 libc.so.6       0x0000003047421ca5 __libc_start_main + 245
21 llc             0x0000000000a11469
Stack dump:
0.    Program arguments: ./llc -mtriple=x86_64-linux-gnux32 -O2 
1.    Running pass 'Function Pass Manager' on module '<stdin>'.
2.    Running pass 'Two-Address instruction pass' on function '@bar'
Aborted
[hjl@gnu-6 stack-1]$</pre>
        </div>
      </p>
      <hr>
      <span>You are receiving this mail because:</span>
      
      <ul>
          <li>You are on the CC list for the bug.</li>
      </ul>
    </body>
</html>