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    <head>
      <base href="http://llvm.org/bugs/" />
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW --- - Use of negative-stride sequences crashes tablegen"
   href="http://llvm.org/bugs/show_bug.cgi?id=19055">19055</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>Use of negative-stride sequences crashes tablegen
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>tools
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>TableGen
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>kuba@mareimbrium.org
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvmbugs@cs.uiuc.edu
          </td>
        </tr>

        <tr>
          <th>Classification</th>
          <td>Unclassified
          </td>
        </tr></table>
      <p>
        <div>
        <pre>This crashes tablegen:

llvm-tblgen -gen-register-info RegisterInfo.td -I llvm/lib/Target -I
llvm/include 

// RegisterInfo.td
include "llvm/Target/Target.td"

def R0  : Register<"r0">;
def R1  : Register<"r1">;
def R2  : Register<"r2">;

// Either one can be first
def RC1  : RegisterClass<"Foo", [i8],  8, (sequence "R%u", 2, 0, -1)>;
def RC2  : RegisterClass<"Foo", [i8],  8, (sequence "R%u", 2, 0)>;

def T : Target {}</pre>
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