<html>
<head>
<base href="http://llvm.org/bugs/" />
</head>
<body><table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - Register coalescer asserts with 'LastMI && "Range must end at a proper instruction"'"
href="http://llvm.org/bugs/show_bug.cgi?id=18261">18261</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>Register coalescer asserts with 'LastMI && "Range must end at a proper instruction"'
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Linux
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Register Allocator
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>james.molloy@arm.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
</td>
</tr>
<tr>
<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>Created <span class=""><a href="attachment.cgi?id=11741" name="attach_11741" title="Bug reproducer">attachment 11741</a> <a href="attachment.cgi?id=11741&action=edit" title="Bug reproducer">[details]</a></span>
Bug reproducer
The attached testcase causes the register coalescer to fall over:
llc: ../lib/CodeGen/RegisterCoalescer.cpp:1834: bool
{anonymous}::JoinVals::resolveConflicts({anonymous}::JoinVals&): Assertion
`LastMI && "Range must end at a proper instruction"' failed.
Reproduce with `llc reduced.ll`
Debug output:
********** SIMPLE REGISTER COALESCING **********
********** Function: entry.thunk
********** JOINING INTERVALS ***********
cond.true107.state0.i:
cond.end103.state0.i:
352B %vreg5<def> = COPY %vreg40; QPR:%vreg5 DPair:%vreg40
Considering merging to QPR with %vreg40 in %vreg5
RHS = %vreg5 [352r,448r:0) 0@352r
LHS = %vreg40 [16r,288B:0)[336B,384r:0) 0@16r
merge %vreg5:0@352r into %vreg40:0@16r --> @16r
erased: 352r %vreg5<def> = COPY %vreg40; QPR:%vreg5 DPair:%vreg40
AllocationOrder(QPR) = [ %Q8 %Q9 %Q10 %Q11 %Q12 %Q13 %Q14 %Q15 %Q0 %Q1 %Q2 %Q3
%Q4 %Q5 %Q6 %Q7 ]
updated: 448B %vreg29<def,dead> = COPY %vreg40; QPR:%vreg29,%vreg40
Joined. Result = %vreg40 [16r,288B:0)[336B,448r:0) 0@16r
368B %vreg3<def> = COPY %vreg40; QPR:%vreg3,%vreg40
Considering merging to QPR with %vreg40 in %vreg3
RHS = %vreg3 [368r,416r:0) 0@368r
LHS = %vreg40 [16r,288B:0)[336B,448r:0) 0@16r
merge %vreg3:0@368r into %vreg40:0@16r --> @16r
erased: 368r %vreg3<def> = COPY %vreg40; QPR:%vreg3,%vreg40
updated: 416B %vreg27<def,dead> = COPY %vreg40; QPR:%vreg27,%vreg40
Joined. Result = %vreg40 [16r,288B:0)[336B,448r:0) 0@16r
384B %vreg0<def> = COPY %vreg40; QPR:%vreg0,%vreg40
Considering merging to QPR with %vreg40 in %vreg0
RHS = %vreg0 [384r,400r:0) 0@384r
LHS = %vreg40 [16r,288B:0)[336B,448r:0) 0@16r
merge %vreg0:0@384r into %vreg40:0@16r --> @16r
erased: 384r %vreg0<def> = COPY %vreg40; QPR:%vreg0,%vreg40
updated: 400B %vreg24<def,dead> = COPY %vreg40; QPR:%vreg24,%vreg40
Joined. Result = %vreg40 [16r,288B:0)[336B,448r:0) 0@16r
400B %vreg24<def,dead> = COPY %vreg40; QPR:%vreg24,%vreg40
Copy is dead.
Deleting dead def 400r %vreg24<def,dead> = COPY %vreg40; QPR:%vreg24,%vreg40
Shrink: %vreg40 [16r,288B:0)[336B,448r:0) 0@16r
live-in at 336B
Shrunk: %vreg40 [16r,288B:0)[336B,448r:0) 0@16r
416B %vreg27<def,dead> = COPY %vreg40; QPR:%vreg27,%vreg40
Copy is dead.
Deleting dead def 416r %vreg27<def,dead> = COPY %vreg40; QPR:%vreg27,%vreg40
Shrink: %vreg40 [16r,288B:0)[336B,448r:0) 0@16r
live-in at 336B
Shrunk: %vreg40 [16r,288B:0)[336B,448r:0) 0@16r
432B %vreg28<def,dead> = COPY %vreg4; QPR:%vreg28,%vreg4
Copy is dead.
Deleting dead def 432r %vreg28<def,dead> = COPY %vreg4; QPR:%vreg28,%vreg4
Shrink: %vreg4 [32r,288B:0)[336B,432r:0) 0@32r
Shrunk: %vreg4 [32r,80r:0) 0@32r
448B %vreg29<def,dead> = COPY %vreg40; QPR:%vreg29,%vreg40
Copy is dead.
Deleting dead def 448r %vreg29<def,dead> = COPY %vreg40; QPR:%vreg29,%vreg40
Shrink: %vreg40 [16r,288B:0)[336B,448r:0) 0@16r
Shrunk: %vreg40 [16r,128r:0) 0@16r
Marshall:
48B %vreg42<def> = COPY %vreg4:dsub_0; DPR:%vreg42 QPR:%vreg4
Considering merging to QPR with %vreg42 in %vreg4:dsub_0
RHS = %vreg42 [48r,160r:0) 0@48r
LHS = %vreg4 [32r,80r:0) 0@32r
merge %vreg42:0@48r into %vreg4:0@32r --> @32r
erased: 48r %vreg42<def> = COPY %vreg4:dsub_0; DPR:%vreg42
QPR:%vreg4
updated: 96B %vreg45:dsub_0<def,read-undef> = COPY %vreg4:dsub_0;
QPR:%vreg45,%vreg4
updated: 112B %vreg45:dsub_1<def> = COPY %vreg4:dsub_0;
QPR:%vreg45,%vreg4
updated: 160B %vreg47:dsub_1<def> = COPY %vreg4:dsub_0;
QPR:%vreg47,%vreg4
Joined. Result = %vreg4 [32r,160r:0) 0@32r
64B %vreg43<def> = COPY %vreg40:dsub_0; DPR:%vreg43 QPR:%vreg40
Considering merging to QPR with %vreg43 in %vreg40:dsub_0
RHS = %vreg43 [64r,176r:0) 0@64r
LHS = %vreg40 [16r,128r:0) 0@16r
merge %vreg43:0@64r into %vreg40:0@16r --> @16r
erased: 64r %vreg43<def> = COPY %vreg40:dsub_0; DPR:%vreg43
QPR:%vreg40
updated: 144B %vreg47:dsub_0<def,read-undef> = COPY %vreg40:dsub_0;
QPR:%vreg47,%vreg40
updated: 176B %vreg48:dsub_0<def,read-undef> = COPY %vreg40:dsub_0;
QPR:%vreg48,%vreg40
Joined. Result = %vreg40 [16r,176r:0) 0@16r
80B %vreg44<def> = COPY %vreg4:dsub_1; DPR:%vreg44 QPR:%vreg4
Considering merging to QPR with %vreg44 in %vreg4:dsub_1
RHS = %vreg44 [80r,208r:0) 0@80r
LHS = %vreg4 [32r,160r:0) 0@32r
merge %vreg44:0@80r into %vreg4:0@32r --> @32r
erased: 80r %vreg44<def> = COPY %vreg4:dsub_1; DPR:%vreg44
QPR:%vreg4
updated: 192B %vreg48:dsub_1<def> = COPY %vreg4:dsub_1;
QPR:%vreg48,%vreg4
updated: 208B %vreg57:dsub_0<def,read-undef> = COPY %vreg4:dsub_1;
QPR:%vreg57,%vreg4
Joined. Result = %vreg4 [32r,208r:0) 0@32r
96B %vreg45:dsub_0<def,read-undef> = COPY %vreg4:dsub_0; QPR:%vreg45,%vreg4
Considering merging to QPR with %vreg4 in %vreg45
RHS = %vreg4 [32r,208r:0) 0@32r
LHS = %vreg45 [96r,112r:1)[112r,112d:0) 0@112r 1@96r
merge %vreg45:1@96r into %vreg4:0@32r --> @32r
conflict at %vreg45:0@112r
taints local %vreg4:0@32r to 208r
tainted lanes used by: %vreg48:dsub_1<def> = COPY %vreg4:dsub_1;
QPR:%vreg48,%vreg4
Interference!
112B %vreg45:dsub_1<def> = COPY %vreg4:dsub_0; QPR:%vreg45,%vreg4
Not coalescable.
128B %vreg46<def> = COPY %vreg40:dsub_1; DPR:%vreg46 QPR:%vreg40
Considering merging to QPR with %vreg46 in %vreg40:dsub_1
RHS = %vreg46 [128r,224r:0) 0@128r
LHS = %vreg40 [16r,176r:0) 0@16r
merge %vreg46:0@128r into %vreg40:0@16r --> @16r
erased: 128r %vreg46<def> = COPY %vreg40:dsub_1; DPR:%vreg46
QPR:%vreg40
updated: 224B %vreg57:dsub_1<def> = COPY %vreg40:dsub_1;
QPR:%vreg57,%vreg40
Joined. Result = %vreg40 [16r,224r:0) 0@16r
144B %vreg47:dsub_0<def,read-undef> = COPY %vreg40:dsub_0;
QPR:%vreg47,%vreg40
Considering merging to QPR with %vreg40 in %vreg47
RHS = %vreg40 [16r,224r:0) 0@16r
LHS = %vreg47 [144r,160r:1)[160r,160d:0) 0@160r 1@144r
merge %vreg47:1@144r into %vreg40:0@16r --> @16r
conflict at %vreg47:0@160r
taints local %vreg40:0@16r to 224r
tainted lanes used by: %vreg57:dsub_1<def> = COPY %vreg40:dsub_1;
QPR:%vreg57,%vreg40
Interference!
160B %vreg47:dsub_1<def> = COPY %vreg4:dsub_0; QPR:%vreg47,%vreg4
Not coalescable.
176B %vreg48:dsub_0<def,read-undef> = COPY %vreg40:dsub_0;
QPR:%vreg48,%vreg40
Considering merging to QPR with %vreg40 in %vreg48
RHS = %vreg40 [16r,224r:0) 0@16r
LHS = %vreg48 [176r,192r:1)[192r,192d:0) 0@192r 1@176r
merge %vreg48:1@176r into %vreg40:0@16r --> @16r
conflict at %vreg48:0@192r
taints local %vreg40:0@16r to 224r
tainted lanes used by: %vreg57:dsub_1<def> = COPY %vreg40:dsub_1;
QPR:%vreg57,%vreg40
Interference!
192B %vreg48:dsub_1<def> = COPY %vreg4:dsub_1; QPR:%vreg48,%vreg4
Considering merging to QPR with %vreg4 in %vreg48
RHS = %vreg4 [32r,208r:0) 0@32r
LHS = %vreg48 [176r,192r:1)[192r,192d:0) 0@192r 1@176r
merge %vreg48:0@192r into %vreg4:0@32r --> @32r
conflict at %vreg48:1@176r
taints local %vreg4:0@32r to 208r
pruned all of %vreg48 at 192r: %vreg48 [176r,192r:1)[192r,192d:0)
0@192r 1@176r
pruned %vreg4 at 176r: %vreg4 [32r,176r:0) 0@32r
erased: 192r %vreg48:dsub_1<def> = COPY %vreg4:dsub_1;
QPR:%vreg48,%vreg4
restoring liveness to 2 points: %vreg48
[32r,176r:0)[176r,192r:1)[192r,192d:0) 0@32r 1@176r
updated: 32B %vreg48<def> = VMOVv4i32 0, pred:14, pred:%noreg;
QPR:%vreg48
updated: 96B %vreg45:dsub_0<def,read-undef> = COPY %vreg48:dsub_0;
QPR:%vreg45,%vreg48
updated: 112B %vreg45:dsub_1<def> = COPY %vreg48:dsub_0;
QPR:%vreg45,%vreg48
updated: 160B %vreg47:dsub_1<def> = COPY %vreg48:dsub_0;
QPR:%vreg47,%vreg48
updated: 208B %vreg57:dsub_0<def,read-undef> = COPY %vreg48:dsub_1;
QPR:%vreg57,%vreg48
Joined. Result = %vreg48 [32r,176r:0)[176r,192r:1)[192r,208r:0) 0@32r
1@176r
208B %vreg57:dsub_0<def,read-undef> = COPY %vreg48:dsub_1;
QPR:%vreg57,%vreg48
Not coalescable.
224B %vreg57:dsub_1<def> = COPY %vreg40:dsub_1; QPR:%vreg57,%vreg40
Considering merging to QPR with %vreg40 in %vreg57
RHS = %vreg40 [16r,224r:0) 0@16r
LHS = %vreg57 [208r,224r:1)[224r,224d:0) 0@224r 1@208r
merge %vreg57:0@224r into %vreg40:0@16r --> @16r
conflict at %vreg57:1@208r
taints local %vreg40:0@16r to 224r
pruned all of %vreg57 at 224r: %vreg57 [208r,224r:1)[224r,224d:0)
0@224r 1@208r
pruned %vreg40 at 208r: %vreg40 [16r,208r:0) 0@16r
erased: 224r %vreg57:dsub_1<def> = COPY %vreg40:dsub_1;
QPR:%vreg57,%vreg40
restoring liveness to 2 points: %vreg57
[16r,208r:0)[208r,224r:1)[224r,224d:0) 0@16r 1@208r
updated: 16B %vreg57<def> = VLD1q64 %vreg41<undef>, 16, pred:14,
pred:%noreg; mem:LD16[undef(align=128)+112](align=16) QPR:%vreg57 GPR:%vreg41
updated: 144B %vreg47:dsub_0<def,read-undef> = COPY %vreg57:dsub_0;
QPR:%vreg47,%vreg57
updated: 176B %vreg48:dsub_0<def> = COPY %vreg57:dsub_0;
QPR:%vreg48,%vreg57
Joined. Result = %vreg57 [16r,208r:0)[208r,224r:1)[224r,224d:0) 0@16r
1@208r
cond.end124.state0.i:
96B %vreg45:dsub_0<def,read-undef> = COPY %vreg48:dsub_0;
QPR:%vreg45,%vreg48
Considering merging to QPR with %vreg48 in %vreg45
RHS = %vreg48 [32r,176r:0)[176r,192r:1)[192r,208r:0) 0@32r 1@176r
LHS = %vreg45 [96r,112r:1)[112r,112d:0) 0@112r 1@96r
merge %vreg45:1@96r into %vreg48:0@32r --> @32r
conflict at %vreg45:0@112r
taints local %vreg48:0@32r to 176r
taints local %vreg48:1@176r to 192r</pre>
</div>
</p>
<hr>
<span>You are receiving this mail because:</span>
<ul>
<li>You are on the CC list for the bug.</li>
</ul>
</body>
</html>