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<base href="http://llvm.org/bugs/" />
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - ARM backend incorrectly limits smlal and umlal instructions to amv6"
href="http://llvm.org/bugs/show_bug.cgi?id=17647">17647</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>ARM backend incorrectly limits smlal and umlal instructions to amv6
</td>
</tr>
<tr>
<th>Product</th>
<td>tools
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Linux
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>llc
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>dpeixott@codeaurora.org
</td>
</tr>
<tr>
<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
</td>
</tr>
<tr>
<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>If I try to compile a simple test that uses inline asm to generate the smlal
and umlal instructions clang fails with an error like this:
$ cat smlal.c
void sfoo(signed a, signed b) {
signed lo;
signed hi;
asm volatile ("smlal %0,%1,%2,%3" : "+&r" (lo), "+&r"(hi) : "r" (a), "r"
(b));
}
void ufoo(unsigned a, unsigned b) {
unsigned lo;
unsigned hi;
asm volatile ("umlal %0,%1,%2,%3" : "+&r" (lo), "+&r"(hi) : "r" (a), "r"
(b));
}
$ clang -O -march=armv4 smlal.c -c
smlal.c:5:17: error: instruction requires: armv6
asm volatile ("smlal %0,%1,%2,%3" : "+&r" (lo), "+&r"(hi) : "r" (a), "r"
(b) : "cc");
^
<inline asm>:1:2: note: instantiated into assembly here
smlal r2,r3,r0,r1
^
smlal.c:11:17: error: instruction requires: armv6
asm volatile ("umlal %0,%1,%2,%3" : "+&r" (lo), "+&r"(hi) : "r" (a), "r"
(b) : "cc");
^
<inline asm>:1:2: note: instantiated into assembly here
umlal r2,r3,r0,r1
If I compile with gcc or disable the integrated assembler (using
-no-integrated-as), it works fine. Looking at the definition for these
instructions in ARMInstrInfo.td I see this:
def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
(ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
IIC_iMAC64,
"smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM,
HasV6]>;
def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
(ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
IIC_iMAC64,
"umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM,
HasV6]>;
Both instructions are defined with Requires<[HasV6]>, but the ARM ARM
(A8.8.178) says that these instructions are available in armv4* and above
(encoding A1).
I also see these definitions in the same file:
def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
(ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p,
cc_out:$s),
4, IIC_iMAC64, [],
(SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo,
GPR:$RHi,
pred:$p, cc_out:$s)>,
Requires<[IsARM, NoV6]>;
def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
(ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p,
cc_out:$s),
4, IIC_iMAC64, [],
(UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo,
GPR:$RHi,
pred:$p, cc_out:$s)>,
Requires<[IsARM, NoV6]>;
I am not sure why these are defined separately for non-v6 targets and what they
are trying to model.</pre>
</div>
</p>
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