<html>
    <head>
      <base href="http://llvm.org/bugs/" />
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW --- - mips disassembly does not sign-extend immediate operand (daddiu, others?)"
   href="http://llvm.org/bugs/show_bug.cgi?id=17539">17539</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>mips disassembly does not sign-extend immediate operand (daddiu, others?)
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>new-bugs
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>FreeBSD
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>new bugs
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>emaste@freebsd.org
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvmbugs@cs.uiuc.edu
          </td>
        </tr>

        <tr>
          <th>Classification</th>
          <td>Unclassified
          </td>
        </tr></table>
      <p>
        <div>
        <pre>I'm adding MIPS support to LLDB and see that daddiu's 16-bit immediate operand
is not interpreted properly:

(lldb) disass
libc.so.7`__raise:
   0x16019e8e0:  daddiu $sp, $sp, 65504
   0x16019e8e4:  sd     $ra, 16($sp)
...

it is a 16-bit signed value; 65504 should be -32

Mips64InstrInfo.td
def DADDiu  : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, IIArith,              
                          immSExt16, add>,                                      
              ADDI_FM<0x19>, IsAsCheapAsAMove;                                  

MipsGenDisassemblerTables.inc
  case 159:
    tmp = fieldFromInstruction(insn, 16, 5);
    if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) ==
MCDisassembler::Fail) return MCDisassembler::Fail;
    tmp = fieldFromInstruction(insn, 21, 5);
    if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) ==
MCDisassembler::Fail) return MCDisassembler::Fail;
    tmp = fieldFromInstruction(insn, 0, 16);
    MI.addOperand(MCOperand::CreateImm(tmp));
    return S;</pre>
        </div>
      </p>
      <hr>
      <span>You are receiving this mail because:</span>
      
      <ul>
          <li>You are on the CC list for the bug.</li>
      </ul>
    </body>
</html>