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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - Implement the SandyBridge/Haswell machine model for x86 SSE4 and AVX."
href="http://llvm.org/bugs/show_bug.cgi?id=17367">17367</a>
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<th>Summary</th>
<td>Implement the SandyBridge/Haswell machine model for x86 SSE4 and AVX.
</td>
</tr>
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<th>Product</th>
<td>new-bugs
</td>
</tr>
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<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>new bugs
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>atrick@apple.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
</td>
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<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>Each instruction in X86InstrSSE.td needs a SchedRW list.
This is a list of types defined in X86Schedule.td.
If new types are added (e.g. WritePopCnt), then a SB/HWWriteRes entry should be
added to X86SchedSandyBridge.td and X86SchedHaswell.td.
Once this is done we can mark the model complete. See this FIXME
def SandyBridgeModel...
// FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
// the scheduler to assign a default model to unrecognized opcodes.
let CompleteModel = 0;
Without this workaround the scheduler asserts because x86 already has itinerary
classes for these instructions, indicating they should be modeled by the
scheduler. Since we use the new machine model for other instructions, it
expects a new machine model for these too.
LLVM ERROR: DefIdx 0 exceeds machine model writes for ...</pre>
</div>
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