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<base href="http://llvm.org/bugs/" />
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<body><table border="1" cellspacing="0" cellpadding="8">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - Code generation problem on ARM (integer comparison)"
href="http://llvm.org/bugs/show_bug.cgi?id=17013">17013</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>Code generation problem on ARM (integer comparison)
</td>
</tr>
<tr>
<th>Product</th>
<td>new-bugs
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>Other
</td>
</tr>
<tr>
<th>OS</th>
<td>Linux
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>new bugs
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>schnetter@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
</td>
</tr>
<tr>
<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>I am using clang 3.3, built on a Raspberry Pi via
{{{
../llvm-3.3/configure --build=armv6-unknown-linux-gnueabihf
--with-cpu=arm1176jzf-s --with-float=hard --with-abi=aapcs-vfp
--enable-targets=arm --enable-optimized --enable-assertions --enable-shared
--prefix=$HOME/llvm-3.3
make REQUIRES_RTTI=1
make REQUIRES_RTTI=1 install
}}}
I am using this compiler to build a simple test code that extracts the sign bit
from a short vector of integers. The test code is
{{{
struct boolvec {
bool v[4];
boolvec& set_elt(int n, bool a) { return v[n]=a, *this; }
boolvec operator!=(boolvec x) const
{
boolvec r;
for (int d=0; d<4; ++d) r.v[d] = v[d]!=x.v[d];
return r;
}
};
struct intvec {
int v[4];
boolvec signbit1() const
{
boolvec r;
for (int d=0; d<4; ++d) r.set_elt(d, v[d]<0);
return r;
}
};
boolvec neq1(boolvec x, boolvec y)
{
return x!=y;
}
boolvec signbit1(intvec x)
{
return x.signbit1();
}
}}}
I build with the options
{{{
clang++ -Ofast -S signbit.cc
}}}
This code is automatically vectorized (congratulations!), but there is a code
generation error. The generated assembler code is
{{{
.syntax unified
.eabi_attribute 6, 6
.eabi_attribute 10, 2
.fpu vfpv2
.eabi_attribute 23, 1
.eabi_attribute 24, 1
.eabi_attribute 25, 1
.eabi_attribute 27, 3
.eabi_attribute 28, 1
.file "signbit.cc"
.text
.globl _Z4neq17boolvecS_
.align 2
.type _Z4neq17boolvecS_,%function
_Z4neq17boolvecS_:
eor r0, r1, r0
bx lr
.Ltmp0:
.size _Z4neq17boolvecS_, .Ltmp0-_Z4neq17boolvecS_
.globl _Z8signbit16intvec
.align 2
.type _Z8signbit16intvec,%function
_Z8signbit16intvec:
lsr r12, r2, #15
mov r2, #16777216
and r3, r2, r3, lsr #7
pkhtb r0, r12, r0, asr #31
mov r2, #256
and r1, r2, r1, lsr #23
orr r0, r0, r3
orr r0, r0, r1
bx lr
.Ltmp1:
.size _Z8signbit16intvec, .Ltmp1-_Z8signbit16intvec
}}}
The error is the following. The integer comparisons to zero (the "v[d] < 0") is
translated to right-shift operations. However, upon vectorization, two of these
shifts are logical (lsr), the two others are arithmetic (asr). As a result, the
bool[4] vector contains the elements {+1,+1,-1,-1} for "all true". I believe
that all elements should be +1.
Since I do not know the internal representation of a boolean true value (maybe
the compiler allows -1 as well?), I also compiled a boolean comparison
operator!=. This shows that this comparison uses "eor", which fails if a true
value is represented as -1.
I thus believe that the "asr" in the pkhtb should be an "lsr" instead.</pre>
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