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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - Many SPARC tests fail with "Bad machine code: Using an undefined physical register" when built with expensive checks enabled"
href="http://llvm.org/bugs/show_bug.cgi?id=16269">16269</a>
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<th>Summary</th>
<td>Many SPARC tests fail with "Bad machine code: Using an undefined physical register" when built with expensive checks enabled
</td>
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<th>Product</th>
<td>new-bugs
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>new bugs
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>baldrick@free.fr
</td>
</tr>
<tr>
<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
</td>
</tr>
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<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>LLVM configured like this: --enable-optimized --enable-assertions
--enable-expensive-checks --enable-debug-symbols
Lots of SPARC codegen tests fail, here's an example:
./Release+Debug+Asserts+Checks/bin/llc <
../llvm/test/CodeGen/SPARC/2007-05-09-JumpTables.ll -march=sparc
--
Exit Code: 1
Command Output (stderr):
--
# After LeafProc Remapping
# Machine code for function foo: Post SSA
Function Live Ins: %I0 in %vreg0
BB#0: derived from LLVM BB %entry
Live Ins: %I0
CMPri %O0, 1, %ICC<imp-def>
BCOND <BB#3>, 12, %ICC<imp-use,kill>
BA <BB#1>
Successors according to CFG: BB#1(16) BB#3(16)
BB#1: derived from LLVM BB %entry
Live Ins: %I0
Predecessors according to CFG: BB#0
CMPri %O0, 0, %ICC<imp-def>
BCOND <BB#9>, 1, %ICC<imp-use,kill>
BA <BB#2>
Successors according to CFG: BB#9(16) BB#2(16)
BB#2: derived from LLVM BB %entry
Live Ins: %I0
Predecessors according to CFG: BB#1
CMPri %O0<kill>, 1, %ICC<imp-def>
BCOND <BB#5>, 1, %ICC<imp-use,kill>
BA <BB#8>
Successors according to CFG: BB#5(16) BB#8(16)
BB#3: derived from LLVM BB %entry
Live Ins: %I0
Predecessors according to CFG: BB#0
CMPri %O0, 2, %ICC<imp-def>
BCOND <BB#6>, 1, %ICC<imp-use,kill>
BA <BB#4>
Successors according to CFG: BB#6(16) BB#4(16)
BB#4: derived from LLVM BB %entry
Live Ins: %I0
Predecessors according to CFG: BB#3
CMPri %O0<kill>, 3, %ICC<imp-def>
BCOND <BB#7>, 1, %ICC<imp-use,kill>
BA <BB#8>
Successors according to CFG: BB#7(16) BB#8(16)
BB#5: derived from LLVM BB %bb4
Predecessors according to CFG: BB#2
%O0<def> = ORri %G0, 2
RETL 8, %O0<imp-use>
BB#6: derived from LLVM BB %bb7
Predecessors according to CFG: BB#3
%O0<def> = ORri %G0, 5
RETL 8, %O0<imp-use>
BB#7: derived from LLVM BB %bb10
Predecessors according to CFG: BB#4
%O0<def> = ORri %G0, 9
RETL 8, %O0<imp-use>
BB#8: derived from LLVM BB %bb14
Predecessors according to CFG: BB#4 BB#2
%O0<def> = SETHIi 0
RETL 8, %O0<imp-use>
BB#9: derived from LLVM BB %UnifiedReturnBlock
Predecessors according to CFG: BB#1
%O0<def> = ORri %G0, 1
RETL 8, %O0<imp-use>
# End machine code for function foo.
*** Bad machine code: Using an undefined physical register ***
- function: foo
- basic block: BB#0 entry (0x2225f60)
- instruction: CMPri %O0, 1, %ICC<imp-def>
- operand 0: %O0
*** Bad machine code: Using an undefined physical register ***
- function: foo
- basic block: BB#1 entry (0x2226698)
- instruction: CMPri %O0, 0, %ICC<imp-def>
- operand 0: %O0
*** Bad machine code: Using an undefined physical register ***
- function: foo
- basic block: BB#2 entry (0x222c050)
- instruction: CMPri %O0<kill>, 1, %ICC<imp-def>
- operand 0: %O0<kill>
*** Bad machine code: Using an undefined physical register ***
- function: foo
- basic block: BB#3 entry (0x22267c8)
- instruction: CMPri %O0, 2, %ICC<imp-def>
- operand 0: %O0
*** Bad machine code: Using an undefined physical register ***
- function: foo
- basic block: BB#4 entry (0x22268f8)
- instruction: CMPri %O0<kill>, 3, %ICC<imp-def>
- operand 0: %O0<kill>
LLVM ERROR: Found 5 machine code errors.
--</pre>
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