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<base href="http://llvm.org/bugs/" />
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - r164281 introduces a lot of errors to X86 atomic lowering"
href="http://llvm.org/bugs/show_bug.cgi?id=15355">15355</a>
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<th>Summary</th>
<td>r164281 introduces a lot of errors to X86 atomic lowering
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: X86
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>zwarich@apple.com
</td>
</tr>
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<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
</td>
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<th>Classification</th>
<td>Unclassified
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<pre>The following tests show errors with the verifier turned on:
LLVM :: CodeGen/X86/atomic-dagsched.ll
LLVM :: CodeGen/X86/atomic-load-store-wide.ll
LLVM :: CodeGen/X86/atomic-minmax-i6432.ll
LLVM :: CodeGen/X86/atomic16.ll
LLVM :: CodeGen/X86/atomic32.ll
LLVM :: CodeGen/X86/atomic64.ll
LLVM :: CodeGen/X86/atomic6432.ll
LLVM :: CodeGen/X86/atomic8.ll
LLVM :: CodeGen/X86/atomic_op.ll
Here's an example from atomic64.ll:
# After ExpandISelPseudos
# Machine code for function atomic_fetch_and64: SSA
BB#0: derived from LLVM BB %0
%vreg0<def> = MOV64ri64i32 5; GR64:%vreg0
%vreg1<def> = MOV64rm %RIP, 1, %noreg, <ga:@sc64>[TF=5], %noreg;
mem:LD8[GOT] GR64:%vreg1
LOCK_AND64mi8 %vreg1, 1, %noreg, 0, %noreg, 3, %EFLAGS<imp-def,dead>;
mem:Volatile LDST8[@sc64] GR64:%vreg1
%RAX<def> = MOV64rm %vreg1, 1, %noreg, 0, %noreg; mem:Volatile LDST8[@sc64]
GR64:%vreg1
Successors according to CFG: BB#1
BB#1: derived from LLVM BB %0
Live Ins: %RAX
Predecessors according to CFG: BB#0 BB#1
%vreg3<def> = COPY %RAX; GR64:%vreg3
%vreg4<def,tied1> = AND64rr %vreg0<tied0>, %vreg3, %EFLAGS<imp-def>;
GR64:%vreg4,%vreg0,%vreg3
%RAX<def> = COPY %vreg3; GR64:%vreg3
LCMPXCHG64 %vreg1, 1, %noreg, 0, %noreg, %vreg4, %RAX<imp-def>,
%EFLAGS<imp-def>, %RAX<imp-use>; mem:Volatile LDST8[@sc64] GR64:%vreg1,%vreg4
JNE_4 <BB#1>, %EFLAGS<imp-use>
Successors according to CFG: BB#1 BB#2
BB#2: derived from LLVM BB %0
Live Ins: %RAX
Predecessors according to CFG: BB#1
%vreg2<def> = COPY %RAX; GR64:%vreg2
LOCK_AND64mr %vreg1, 1, %noreg, 0, %noreg, %vreg2<kill>,
%EFLAGS<imp-def,dead>; mem:Volatile LDST8[@sc64] GR64:%vreg1,%vreg2
RET
# End machine code for function atomic_fetch_and64.
*** Bad machine code: Missing mayStore flag ***
- function: atomic_fetch_and64
- basic block: BB#0 (0x7fdff182ffa0)
- instruction: %RAX<def> = MOV64rm %vreg1, 1, %noreg, 0, %noreg; mem:Volatile
LDST8[@sc64] GR64:%vreg1
*** Bad machine code: MBB has allocable live-in, but isn't entry or
landing-pad. ***
- function: atomic_fetch_and64
- basic block: BB#1 (0x7fdff1830830)
*** Bad machine code: MBB has allocable live-in, but isn't entry or
landing-pad. ***
- function: atomic_fetch_and64
- basic block: BB#2 (0x7fdff18308d8)
LLVM ERROR: Found 3 machine code errors.</pre>
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