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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [x86 disassembler] add support for adcx and adox (Intel ADX instructions)"
href="http://llvm.org/bugs/show_bug.cgi?id=15235">15235</a>
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<th>Summary</th>
<td>[x86 disassembler] add support for adcx and adox (Intel ADX instructions)
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: X86
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>kkhoo@perfwizard.com
</td>
</tr>
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<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
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<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>The "Intel® Architecture Instruction Set Extensions Programming Reference"
dated Aug 2012 ( <a href="http://software.intel.com/en-us/avx/">http://software.intel.com/en-us/avx/</a> ) includes new
instructions scheduled for inclusion with either Haswell (scheduled for 2013)
or Broadwell (scheduled for 2014).
This includes:
ADCX — Unsigned Integer Addition of Two Operands with Carry Flag
66 0F 38 F6 /r ADCX r32, r/m32
REX.w + 66 0F 38 F6 /r ADCX r64, r/m64
and
ADOX — Unsigned Integer Addition of Two Operands with Overflow Flag
F3 0F 38 F6 /r ADOX r32, r/m32
REX.w + F3 0F 38 F6 /r ADOX r64, r/m64
With llvm-mc (r174572), these return "invalid instruction encoding". For
example:
$ echo '0x66 0x0f 0x38 0xf6 0xc0' | ./Debug+Asserts/bin/llvm-mc -disassemble
-triple=x86_64
.section __TEXT,__text,regular,pure_instructions
data16
<stdin>:1:11: warning: invalid instruction encoding
0x66 0x0f 0x38 0xf6 0xc0
^</pre>
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