[llvm-bugs] [Bug 36894] New: [X86] SLM Model doesn't account for load latency for SSE42/AES/CLMUL classes

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36894

            Bug ID: 36894
           Summary: [X86] SLM Model doesn't account for load latency for
                    SSE42/AES/CLMUL classes
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org
            Blocks: 32325

e.g.

def : WriteRes<WriteCLMul, [SLM_FPC_RSV0]> {
  let Latency = 10;
  let ResourceCycles = [10];
}
def : WriteRes<WriteCLMulLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
  let Latency = 10;
  let ResourceCycles = [10, 1];
}

I'd expect the WriteCLMulLd Latency to at least be 13cy (default LoadLat), same
for the others.


Referenced Bugs:

https://bugs.llvm.org/show_bug.cgi?id=32325
[Bug 32325] [META][X86] Improve implementation and use of X86 scheduler models
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