[llvm-bugs] [Bug 36662] New: [llvm-mca] [Scheduling Model] Let models optionally specify register files.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36662

            Bug ID: 36662
           Summary: [llvm-mca] [Scheduling Model] Let models optionally
                    specify register files.
           Product: new-bugs
           Version: unspecified
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: andrea.dibiagio at gmail.com
                CC: llvm-bugs at lists.llvm.org

The goal of this task is to describe to the tool which register files are
available on the CPU.

At the moment, llvm-mca assumes a single register file with an unbounded number
of temporary registers. Users can limit the number of temporary registers
available for register renaming using flag -register-file-size=<uint>.
Knowing how many temporaries are available for register renaming allows the
tool to predict dispatch stalls caused by the lack of temporary registers.

The idea is to extend the scheduling model framework introducing new
abstractions to describe register files.
In particular, the model should be able to describe:
 - The number of temporaries in each register file.
 - How register classes map to register files.

If a target doesn't specify a register file, then by default we assume a single
register file with an unbounded number of registers.

llvm-mca will have to query the model to discover which register files are
available. This would require a few changes in class RegisterFile (Dispatch.h).

Optionally, the tablegen backend should check that register files are disjoint
(i.e. register classes don't specify the same registers).

This would enable a more accurate description of processors like Jaguar
(BtVer2), where the floating point unit implements a coprocessor model with its
own register file.

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