[llvm-bugs] [Bug 38368] New: GlobalISel: Investigate an efficient way to ensure load/store orderings

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=38368

            Bug ID: 38368
           Summary: GlobalISel: Investigate an efficient way to ensure
                    load/store orderings
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: GlobalISel
          Assignee: unassignedbugs at nondot.org
          Reporter: aemerson at apple.com
                CC: llvm-bugs at lists.llvm.org

Load/store ordering needs some thought, as we currently don’t have a way to
easily check at the MI level what the ordering requirements are on a set of
memory operations. SelectionDAG uses the chains to ensure that they’re
scheduled to respect the orderings. How to achieve the same thing remains an
open question for GlobalISel.

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