[llvm-bugs] [Bug 36280] New: [SLPVectorizer] 2-way parallel vectorization hurts perf on x86

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36280

            Bug ID: 36280
           Summary: [SLPVectorizer] 2-way parallel vectorization hurts
                    perf on x86
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Transformation Utilities
          Assignee: unassignedbugs at nondot.org
          Reporter: spatel+llvm at rotateright.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 19830
  --> https://bugs.llvm.org/attachment.cgi?id=19830&action=edit
himeno.c source file

This is a reduction from the Himeno benchmark (attached). In the actual
benchmark, we lose 6% performance on AMD Jaguar when using SLP vectorization
because the extra insert/extract ops cost more than the savings from combining
2 scalar loads and 2 scalar fmul.

(p[1] * x) + z + (p[2] * y)

---------------------------------------------------------------------------

target triple = "x86_64-unknown-unknown"

define float @jacobi(float* %p, float %x, float %y, float %z) {
  %gep1 = getelementptr float, float* %p, i64 1
  %gep2 = getelementptr float, float* %p, i64 2
  %p1 = load float, float* %gep1
  %p2 = load float, float* %gep2
  %mul1 = fmul float %p1, %x
  %mul2 = fmul float %p2, %y
  %add1 = fadd float %mul1, %z
  %add2 = fadd float %mul2, %add1
  ret float %add2
}

$ ./opt -slp-vectorizer  minnn.ll -S 

define float @jacobi(float* %p, float %x, float %y, float %z) {
  %gep1 = getelementptr float, float* %p, i64 1
  %gep2 = getelementptr float, float* %p, i64 2
  %1 = bitcast float* %gep1 to <2 x float>*
  %2 = load <2 x float>, <2 x float>* %1, align 4
  %3 = insertelement <2 x float> undef, float %x, i32 0
  %4 = insertelement <2 x float> %3, float %y, i32 1
  %5 = fmul <2 x float> %4, %2
  %6 = extractelement <2 x float> %5, i32 0
  %add1 = fadd float %6, %z
  %7 = extractelement <2 x float> %5, i32 1
  %add2 = fadd float %7, %add1
  ret float %add2
}

-----------------------------------------------------------------------

The x86 AVX code looks like this without SLP:
        vmulss  4(%rdi), %xmm0, %xmm0
        vmulss  8(%rdi), %xmm1, %xmm1
        vaddss  %xmm2, %xmm0, %xmm0
        vaddss  %xmm0, %xmm1, %xmm0

And this with SLP:
        vmovsd  4(%rdi), %xmm3          # xmm3 = mem[0],zero
        vinsertps       $16, %xmm1, %xmm0, %xmm0 # xmm0 =
xmm0[0],xmm1[0],xmm0[2,3]
        vmulps  %xmm3, %xmm0, %xmm0
        vaddss  %xmm2, %xmm0, %xmm1
        vmovshdup       %xmm0, %xmm0    # xmm0 = xmm0[1,1,3,3]
        vaddss  %xmm1, %xmm0, %xmm0

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