[llvm-bugs] [Bug 34577] New: [X86] Bug in shuffle-to-zero-extend transformation

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=34577

            Bug ID: 34577
           Summary: [X86] Bug in shuffle-to-zero-extend transformation
           Product: libraries
           Version: trunk
          Hardware: All
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: ayman.musa at intel.com
                CC: llvm-bugs at lists.llvm.org

X86ISD::VZEXT node is defined to work on integer types only.

In the following IR code:

define internal fastcc <8 x float> @test(<8 x float> %inp3, <8 x float> %inp6,
<8 x float> %inp9) #0 {
entry:
  %shuf6 = shufflevector <8 x float> %inp3, <8 x float> %inp9, <8 x i32> <i32
1, i32 10, i32 11, i32 13, i32 2, i32 13, i32 5, i32 0>
  %sel6 = select <8 x i1> <i1 false, i1 true, i1 true, i1 false, i1 true, i1
false, i1 true, i1 false>, <8 x float> %shuf6, <8 x float> zeroinitializer
  %shuf7 = shufflevector <8 x float> zeroinitializer, <8 x float> %sel6, <8 x
i32> <i32 6, i32 11, i32 6, i32 15, i32 12, i32 11, i32 1, i32 3>
  %shuf8 = shufflevector <8 x float> %inp6, <8 x float> %shuf7, <8 x i32> <i32
15, i32 10, i32 7, i32 2, i32 12, i32 undef, i32 3, i32 2>
  ret <8 x float> %shuf8
}

the input for the extract_subvector instruction should be bitcasted to integer
type type before feeding it to zero-extend.

> ../../build/bin/llc -mattr=+avx2 test.ll -o test.s

LLVM ERROR: Cannot select: t126: v4i64 = X86ISD::VZEXT t125
  t125: v4f32 = extract_subvector t2, Constant:i64<0>
    t2: v8f32,ch = CopyFromReg t0, Register:v8f32 %vreg0
      t1: v8f32 = Register %vreg0
    t124: i64 = Constant<0>
In function: test

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