[llvm-bugs] [Bug 33545] New: Tablegen does not generate the correct operand types for the MCInstrDesc:s

via llvm-bugs llvm-bugs at lists.llvm.org
Wed Jun 21 07:34:21 PDT 2017


https://bugs.llvm.org/show_bug.cgi?id=33545

            Bug ID: 33545
           Summary: Tablegen does not generate the correct operand types
                    for the MCInstrDesc:s
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Target Description Classes
          Assignee: unassignedbugs at nondot.org
          Reporter: paulsson at linux.vnet.ibm.com
                CC: llvm-bugs at lists.llvm.org

I noticed that it seems that all the addressing operands of the SystemZ backend
instructions seem to all have the UNKNOWN type, which is a bit odd. I was
expecting to see either REGISTER or IMMEDIATE.

For example:

lib/Target/SystemZ/SystemZGenInstrInfo.inc:

{ 1142,       4,      1,      6,      41,    
0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x10dULL, nullptr,
nullptr, OperandInfo30, -1 ,nullptr },  // Inst #1142 = LG  (Load 64 bits from
memory)

static const MCOperandInfo OperandInfo30[] = { { SystemZ::GR64BitRegClassID, 0,
MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0,
MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, {
SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };

It seems for all AddressingMode operands, these are all UNKNOWN instead of
OPERAND_REGISTER / OPERAND_IMMEDIATE...

Is this a bug in tablegen, or is it possible to fix it in the SystemZ
implementation?

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