[llvm-bugs] [Bug 35589] New: [X86] Scheduling information missing for DIV8r/IDIV8r

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=35589

            Bug ID: 35589
           Summary: [X86] Scheduling information missing for DIV8r/IDIV8r
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: craig.topper at gmail.com
                CC: llvm-bugs at lists.llvm.org

We have scheduling info for DIV8m/IDIV8m, but not the register version

>From schedcov.py:
DIV8r, WriteIDiv, , , WriteDiv8, , , , ZnWriteDiv8
IDIV8r, WriteIDiv, , , WriteIDiv8, , , , ZnWriteDiv8

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