[llvm-bugs] [Bug 35561] New: [AMDGPU][MC] 256- and 512-bit tuples of ttmp registers should be supported

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=35561

            Bug ID: 35561
           Summary: [AMDGPU][MC] 256- and 512-bit tuples of ttmp registers
                    should be supported
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AMDGPU
          Assignee: unassignedbugs at nondot.org
          Reporter: dpreobrazhensky at luxoft.com
                CC: llvm-bugs at lists.llvm.org

Currently assembler supports only 64- and 128-bit ttmp tuples.

Examples of failing tests (gfx9):

s_load_dwordx8 ttmp[8:15], s[2:3], s0
s_buffer_load_dwordx16 ttmp[0:15], s[4:7], s0

-- 
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20171207/47f07549/attachment.html>