[llvm-bugs] [Bug 30606] New: [ppc] Store forwarding caused by use after copy

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=30606

            Bug ID: 30606
           Summary: [ppc] Store forwarding caused by use after copy
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: PowerPC
          Assignee: unassignedbugs at nondot.org
          Reporter: carrot at google.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Compile following source code with options

 -m64 -O2 -mvsx -mcpu=power8 

struct S { 
  char* p1; 
  char* p2; 
  char* p3; 
  char* p4; 
};

void bar(struct S*);

void foo(struct S *p) {
  struct S s = *p; 
  if (s.p1 > s.p2)
    return;
  bar(&s);
}

LLVM generates:

foo:                                    # @foo
.Lfunc_begin0:
.Lfunc_gep0:
        addis 2, 12, .TOC.-.Lfunc_gep0 at ha
        addi 2, 2, .TOC.-.Lfunc_gep0 at l
.Lfunc_lep0:
        .localentry     foo, .Lfunc_lep0-.Lfunc_gep0
# BB#0:                                 # %entry
        mflr 0
        std 31, -8(1)
        std 0, 16(1)
        stdu 1, -144(1)
        li 4, 16
        mr 31, 1
        lxvd2x 0, 3, 4           // copy
        addi 5, 31, 96 
        stxvd2x 0, 5, 4          // copy
        ori 2, 2, 0
        lxvd2x 0, 0, 3           // copy
        stxvd2x 0, 0, 5          // copy
        ori 2, 2, 0
        ld 3, 96(31)             // load again
        ld 12, 104(31)           // load again
        cmpld    3, 12
        bgt      0, .LBB0_2
# BB#1:                                 # %if.end
        addi 3, 31, 96
        bl bar 
        nop
.LBB0_2:                                # %cleanup
        addi 1, 1, 144 
        ld 0, 16(1)
        ld 31, -8(1)
        mtlr 0
        blr

First it uses lxvd2x/stxvd2x instructions to copy *p to s, after that it loads
s.p1 and s.p2 immediately, it triggers the slow store forwarding.

A faster code should load p->p1 and p->p2 instead. Or copy through general
registers, then reuse those values.

A minor problem is the scheduling of lxvd2x/stxvd2x instructions.

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