[llvm-bugs] [Bug 27046] New: PowerPC64: Machine code verifier failure - Using an undefined physical register

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=27046

            Bug ID: 27046
           Summary: PowerPC64: Machine code verifier failure - Using an
                    undefined physical register
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: PowerPC
          Assignee: unassignedbugs at nondot.org
          Reporter: anton at samba.org
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Created attachment 16077
  --> https://llvm.org/bugs/attachment.cgi?id=16077&action=edit
Test case

I'm seeing test case failures in Julia where the LLVM machine code verifier
fails.

I used llc -verify-machineinstrs to find a similar issue in C code, which
allowed me to produce a cut down testcase:

# llc -O2 -verify-machineinstrs wrong1.ll

# After Peephole Optimizations
# Machine code for function fn1: SSA

BB#0: derived from LLVM BB %0
    ADJCALLSTACKDOWN 96, %R1<imp-def,dead>, %R1<imp-use>
    BL8_NOP <ga:@fn2>, <regmask %CR2 %CR3 %CR4 %F14 %F15 %F16 %F17 %F18 %F19
%F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %R14 %R15 %R16 %R17
%R18 %R19 %R20 %R21 %R22 %R23 %R24 %R25 %R26 %R27 %R28 %R29 %R30 %R31 %V20 %V21
%V22 %V23 %V24 %V25 %V26 %V27 %V28 %V29 %V30 %V31 %VF20 %VF21 %VF22 %VF23 %VF24
%VF25 %VF26 %VF27 %VF28 %VF29 %VF30 %VF31 %X14 %X15 %X16 %X17 %X18 %X19 %X20
%X21 %X22 %X23 %X24 %X25 %X26 %X27 %X28 %X29 %X30 %X31 %CR2EQ %CR3EQ %CR4EQ
%CR2GT %CR3GT %CR4GT %CR2LT %CR3LT %CR4LT %CR2UN %CR3UN %CR4UN>,
%LR8<imp-def,dead>, %RM<imp-use>, %X2<imp-use>, %R1<imp-def>, %X3<imp-def>
    ADJCALLSTACKUP 96, 0, %R1<imp-def,dead>, %R1<imp-use>
    %vreg4<def> = COPY %X3; G8RC:%vreg4
    %vreg5<def> = COPY %vreg4:sub_32; GPRC:%vreg5 G8RC:%vreg4
    %vreg6<def> = MULLI %vreg5<kill>, 208; GPRC:%vreg6,%vreg5
    %vreg8<def> = IMPLICIT_DEF; G8RC:%vreg8
    %vreg7<def,tied1> = INSERT_SUBREG %vreg8<tied0>, %vreg6<kill>, sub_32;
G8RC:%vreg7,%vreg8 GPRC:%vreg6
    %vreg9<def> = RLDICL %vreg7<kill>, 0, 32; G8RC:%vreg9,%vreg7
    %vreg10<def> = ANDIo8 %vreg9, 65520, %CR0<imp-def,dead>;
G8RC:%vreg10,%vreg9
    %vreg11<def> = COPY %CR0; CRRC:%vreg11
    BCC 68, %vreg11<kill>, <BB#1>; CRRC:%vreg11
    Successors according to CFG: BB#3(0x30000000 / 0x80000000 = 37.50%)
BB#1(0x50000000 / 0x80000000 = 62.50%)

BB#3: 
    Predecessors according to CFG: BB#0
    %vreg3<def> = CRSET; CRBITRC:%vreg3
    B <BB#2>
    Successors according to CFG: BB#2(?%)

BB#1: derived from LLVM BB %7
    Predecessors according to CFG: BB#0
    %vreg0<def> = EXTSH8 %vreg9; G8RC:%vreg0,%vreg9
    %vreg12<def> = ADDIStocHA %X2, <ga:@a>; G8RC_and_G8RC_NOX0:%vreg12
    %vreg13<def> = LDtocL <ga:@a>, %vreg12<kill>; mem:LD8[GOT]
G8RC_and_G8RC_NOX0:%vreg13,%vreg12
    %vreg14<def> = LWA 0, %vreg13<kill>; mem:LD4[@a](tbaa=!2) G8RC:%vreg14
G8RC_and_G8RC_NOX0:%vreg13
    %vreg15<def> = DIVDo %vreg14<kill>, %vreg0, %CR0<imp-def>;
G8RC:%vreg15,%vreg14,%vreg0
    %vreg16<def> = COPY %CR0<kill>; CRRC:%vreg16
    %vreg17<def> = COPY %vreg16:sub_eq; CRBITRC:%vreg17 CRRC:%vreg16
    %vreg1<def> = CRNOR %vreg17, %vreg17; CRBITRC:%vreg1,%vreg17,%vreg17
    Successors according to CFG: BB#2(?%)

BB#2: derived from LLVM BB %12
    Predecessors according to CFG: BB#1 BB#3
    %vreg2<def> = PHI %vreg3, <BB#3>, %vreg1, <BB#1>;
CRBITRC:%vreg2,%vreg3,%vreg1
    %vreg18<def> = LI 0; GPRC_and_GPRC_NOR0:%vreg18
    %vreg19<def> = LI 1; GPRC_and_GPRC_NOR0:%vreg19
    %vreg20<def> = ISEL %vreg19, %vreg18, %vreg2; GPRC:%vreg20
GPRC_and_GPRC_NOR0:%vreg19,%vreg18 CRBITRC:%vreg2
    %vreg21<def> = ADDIStocHA %X2, <ga:@b>; G8RC_and_G8RC_NOX0:%vreg21
    %vreg22<def> = LDtocL <ga:@b>, %vreg21<kill>; mem:LD8[GOT]
G8RC_and_G8RC_NOX0:%vreg22,%vreg21
    STW %vreg20<kill>, 0, %vreg22<kill>; mem:ST4[@b](tbaa=!2) GPRC:%vreg20
G8RC_and_G8RC_NOX0:%vreg22
    %vreg23<def> = LI8 0; G8RC:%vreg23
    %X3<def> = COPY %vreg23; G8RC:%vreg23
    BLR8 %LR8<imp-use>, %RM<imp-use>, %X3<imp-use>

# End machine code for function fn1.

*** Bad machine code: Using an undefined physical register ***
- function:    fn1
- basic block: BB#0  (0x10024f274a0)
- instruction: %vreg11<def> = COPY
- operand 1:   %CR0
LLVM ERROR: Found 1 machine code errors.

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