[llvm-bugs] [Bug 13275] Problem when passing small vector as parameter for ARM + NEON target

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=13275

Renato Golin <renato.golin at linaro.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
                 CC|                            |renato.golin at linaro.org
         Resolution|---                         |INVALID

--- Comment #2 from Renato Golin <renato.golin at linaro.org> ---
Funny enough, GAS is now perfectly ok with the syntax, and throws errors if we
use 64:

$ arm-none-eabi-as -march=armv7-a -mcpu=cortex-a9 -mfpu=neon -mfloat-abi=hard
bar.s 
bar.s: Assembler messages:
bar.s:30: Error: unsupported alignment for instruction -- `vld1.16
{d16[0]},[r1:64]'
bar.s:31: Error: unsupported alignment for instruction -- `vld1.16
{d17[0]},[r0:64]'

While LLVM-MC seems to be on the same page:

$ echo "vld1.16{d16[0]}, [r1:64]" | llvm-mc -triple=armv7-a-linux-gnueabihf
-mcpu=cortex-a9 -show-encoding
    .text
<stdin>:1:22: error: alignment must be 16 or omitted
vld1.16{d16[0]}, [r1:64]
                     ^

Even though the ARM ARM (A8.8.320) seems to imply it should be in bits, both
tools want in bytes, and identical to the element size (which makes some
sense).

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