[llvm-bugs] [Bug 26161] New: [GlobalISel] Value to vreg during IR to MachineInstr translation for aggregate type

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=26161

            Bug ID: 26161
           Summary: [GlobalISel] Value to vreg during IR to MachineInstr
                    translation for aggregate type
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: qcolombet at apple.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

The design to handle aggregate types during IR translation in GlobalISel will
need to be revisited to at least acknowledge that we choose the right approach.

At first, this is not critical that we don’t support aggregate types, thus a
simple mapping one Value* to one Vreg is perfectly fine.

When we would add the support for such types, we have basically two options:
1. Replicate SDAG solution, i.e., more or less map one Value* to a list of
Vregs (one Vreg per component).
2. Keep the mapping simple, i.e., one Value* to one (big) Vreg.

The pros and cons are discussed in the following thread:
http://lists.llvm.org/pipermail/llvm-dev/2016-January/094049.html

Although #2 seems preferable, we don’t have any actual experience on how well
we would be to optimize this representation.

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