[llvm-bugs] [Bug 26092] New: [ppc] extra memory accesses caused by inaccurate alias info

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=26092

            Bug ID: 26092
           Summary: [ppc] extra memory accesses caused by inaccurate alias
                    info
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: PowerPC
          Assignee: unassignedbugs at nondot.org
          Reporter: carrot at google.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Created attachment 15596
  --> https://llvm.org/bugs/attachment.cgi?id=15596&action=edit
testcase

Compile the attached source code with following command line

~/llvm/obj/bin/clang++ --target=powerpc64le-grtev4-linux-gnu
-fno-strict-aliasing -mcpu=power8 -O2 -c t7.cc -o t7.o

I got:


0000000000000060 <_Z3quxRK2PBS1_PS_>:
  60:   00 00 4c 3c     addis   r2,r12,0
  64:   00 00 42 38     addi    r2,r2,0
  68:   a6 02 08 7c     mflr    r0  
  6c:   f8 ff e1 fb     std     r31,-8(r1)
  70:   10 00 01 f8     std     r0,16(r1)
  74:   81 ff 21 f8     stdu    r1,-128(r1)
  78:   78 0b 3f 7c     mr      r31,r1
  7c:   68 00 bf fb     std     r29,104(r31)
  80:   78 1b 7d 7c     mr      r29,r3
  84:   60 00 7f 38     addi    r3,r31,96
  88:   70 00 df fb     std     r30,112(r31)
  8c:   78 23 9e 7c     mr      r30,r4
  90:   60 00 bf f8     std     r5,96(r31)
  94:   01 00 00 48     bl      94 <_Z3quxRK2PBS1_PS_+0x34>
  98:   60 00 7f e8     ld      r3,96(r31)              // A1
  9c:   10 00 bd e8     ld      r5,16(r29)
  a0:   10 00 de e8     ld      r6,16(r30)
  a4:   18 00 80 39     li      r12,24
  a8:   08 00 83 80     lwz     r4,8(r3)               // B1
  ac:   14 2a a6 7c     add     r5,r6,r5
  b0:   01 00 84 60     ori     r4,r4,1                // B2
  b4:   08 00 83 90     stw     r4,8(r3)               // B3
  b8:   10 00 a3 f8     std     r5,16(r3)
  bc:   00 00 42 60     ori     r2,r2,0
  c0:   18 64 1d 7c     lxsspx  vs0,r29,r12
  c4:   60 00 9f e8     ld      r4,96(r31)              // A2
  c8:   18 64 3e 7c     lxsspx  vs1,r30,r12
  cc:   70 00 df eb     ld      r30,112(r31)
  d0:   68 00 bf eb     ld      r29,104(r31)
  d4:   08 00 a4 80     lwz     r5,8(r4)              // C1
  d8:   00 08 00 f0     xsaddsp vs0,vs0,vs1
  dc:   02 00 a5 60     ori     r5,r5,2               // C2
  e0:   08 00 a4 90     stw     r5,8(r4)              // C3
  e4:   18 65 04 7c     stxsspx vs0,r4,r12
  e8:   80 00 21 38     addi    r1,r1,128
  ec:   10 00 01 e8     ld      r0,16(r1)
  f0:   f8 ff e1 eb     ld      r31,-8(r1)
  f4:   a6 03 08 7c     mtlr    r0  
  f8:   20 00 80 4e     blr

Instructions A1 and A2 load pointer c two times.
Instructions B1 B2 B3 load/modify/write field _has_bits_, instructions C1 C2 C3
do similar thing. 

With accurate alias information, address of pointer c can't be aliased with the
object pointed by c (although function bar escapes t, it is only returned to
function foo, and not actually used in foo.), so instructions A2 and C1 are
redundant.

GCC can generate better code without these extra memory loads.

In one of our internal application, this problem causes 6x slow down compared
with gcc.

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