[llvm-bugs] [Bug 31369] New: Register allocator uses reserved register on MIPS

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=31369

            Bug ID: 31369
           Summary: Register allocator uses reserved register on MIPS
           Product: new-bugs
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: simon.dardis at imgtec.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Created attachment 17752
  --> https://llvm.org/bugs/attachment.cgi?id=17752&action=edit
Reproduction case as test.

The issue demonstrated in the attached test case is the use of a reserved
single precision floating point register. One of MIPS' floating point ABIs
requires that the odd single precision registers are not used.

>From the test case (lines 17-21):
  %5 = load float, float * @f1
  %6 = insertelement <4 x float> undef,    float %5, i32 0
  %7 = insertelement <4 x float> %6,    float %5, i32 1
  %8 = insertelement <4 x float> %7,    float %5, i32 2
  %9 = insertelement <4 x float> %8,    float %5, i32 3


After the processing of implicit defs:

..
96B             %vreg4<def> = LWC1 %vreg3<kill>, <ga:@f1>[TF=5];
mem:LD4[@f1](dereferenceable) FGR32:%vreg4 GPR32:%vreg3
112B            %vreg12:sub_lo<def,read-undef> = COPY %vreg4<kill>;
MSA128W:%vreg12 FGR32:%vreg4
128B            %vreg5<def> = SPLATI_W %vreg12<kill>, 0; MSA128W:%vreg5,%vreg12
..

This code is correct as FGR32 has the correct reserved registers.

After the joining live intervals:

..
96B             %vreg12:sub_lo<def,read-undef> = LWC1 %vreg3, <ga:@f1>[TF=5];
mem:LD4[@f1](dereferenceable) MSA128B:%vreg12 GPR32:%vreg3
128B            %vreg5<def> = SPLATI_W %vreg12, 0; MSA128W:%vreg5
MSA128B:%vreg12
..

Here, the copy has been coalesced into the load which is using the sub_lo of a
register in the MSA128B class.

The greedy register allocator then bases the allocation choice on the MSA128B
register class and picks an odd MSA register %W1 and uses the corresponding
single precision subregister $F1:

..
selectOrSplit MSA128B:%vreg12 [96r,128r:0)  0 at 96r w=INF
assigning %vreg12 to %W1: F1 [96r,128r:0)  0 at 96r F_HI1 [96r,128r:0)  0 at 96r
..


If the output is emitted directly as an object file, it silently succeeds.
Passing the resulting assembly to external assembler results in a bad code.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20161214/5656be98/attachment.html>