[llvm-bugs] [Bug 24942] New: [instcombine] vector math/logic doesn't get the same bitwise optimizations as scalar

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=24942

            Bug ID: 24942
           Summary: [instcombine] vector math/logic doesn't get the same
                    bitwise optimizations as scalar
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Scalar Optimizations
          Assignee: unassignedbugs at nondot.org
          Reporter: spatel+llvm at rotateright.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Hole in SimplifyDemandedBits, computeKnownBits, or something else?

"31" and "2" don't have any special meaning here; lots of other constant pairs
could illustrate the same point:

define i32 @lshr_and_i32(i32 %x) {
  %lshr = lshr i32 %x, 31
  %and = and i32 %lshr, 2
  ret i32 %and
}

define <2 x i32> @lshr_and_v2i32(<2 x i32> %x) {
  %lshr = lshr <2 x i32> %x, <i32 31, i32 31>
  %and = and <2 x i32> %lshr, <i32 2, i32 2>
  ret <2 x i32> %and
}

$ ./opt -instcombine demand.ll -S 

define i32 @lshr_and_i32(i32 %x) {
  ret i32 0
}

define <2 x i32> @lshr_and_v2i32(<2 x i32> %x) {
  %lshr = lshr <2 x i32> %x, <i32 31, i32 31>
  %and = and <2 x i32> %lshr, <i32 2, i32 2>
  ret <2 x i32> %and
}

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