[llvm-bugs] [Bug 24724] New: MI Serialization - inconsistent implicit operand ordering assumptions

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=24724

            Bug ID: 24724
           Summary: MI Serialization - inconsistent implicit operand
                    ordering assumptions
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: hfinkel at anl.gov
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Created attachment 14844
  --> https://llvm.org/bugs/attachment.cgi?id=14844&action=edit
MIR

Running the attached IR through llc using:

$ llc -o test.s test.ll -stop-after=machine-combiner > test.orig.mir

produces the attached IR. However, trying to ingest that MIR using:

$ llc -o test.s test.orig.mir -start-after=machine-combiner
-stop-after=machine-cse

yields this error:

error: test.orig.mir:64:39: expected an implicit register operand 'implicit
%rm'
    BLR8 implicit %lr8, implicit %rm, implicit %x3
                                      ^
Changing the line as serialized:

  BLR8 implicit %lr8, implicit %rm, implicit %x3

to this:

  BLR8 implicit %x3, implicit %lr8, implicit %rm

allows the ingest to succeed. If MIR parsing requires a specific order of
implicit operands, it should always output them that way. Better, it should not
have this ordering requirement.

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