[LLVMbugs] [Bug 21801] ARM64: Assertion failed: ((BiggerPattern || (Srl_imm > 0 && Srl_imm < VT.getSizeInBits())) && "bad amount in shift node!")

[bugzilla-daemon at llvm.org]

https://llvm.org/bugs/show_bug.cgi?id=21801

Matthias Braun <matze at braunis.de> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
                 CC|                            |matze at braunis.de
         Resolution|---                         |FIXED
           Assignee|unassignedbugs at nondot.org   |matze at braunis.de

--- Comment #1 from Matthias Braun <matze at braunis.de> ---
This has been fixed a while ago in r230355

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