[llvm-bugs] [Bug 25808] New: [InstCombine] canonicalize extractelement reductions with shuffles

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=25808

            Bug ID: 25808
           Summary: [InstCombine] canonicalize extractelement reductions
                    with shuffles
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Scalar Optimizations
          Assignee: unassignedbugs at nondot.org
          Reporter: spatel+llvm at rotateright.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Hal suggested something like this in D15250:
http://reviews.llvm.org/D15250

$ cat reduction.c 
typedef int v4i __attribute__((vector_size(16)));
int foo(v4i x) {
  return x[0] + x[1] + x[2] + x[3];
}

$ ./clang -O1 reduction.c -S -o - -emit-llvm
...
define i32 @foo(<4 x i32> %x) #0 {
entry:
  %vecext = extractelement <4 x i32> %x, i32 0
  %vecext1 = extractelement <4 x i32> %x, i32 1
  %add = add nsw i32 %vecext, %vecext1
  %vecext2 = extractelement <4 x i32> %x, i32 2
  %add3 = add nsw i32 %add, %vecext2
  %vecext4 = extractelement <4 x i32> %x, i32 3
  %add5 = add nsw i32 %add3, %vecext4
  ret i32 %add5
}

InstCombine should be able to transform this into vector math + shuffles to
reduce the instruction count for any vector with 4+ elements:

  %shuf1 = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 2, i32
3, i32 undef, i32 undef>  ; shift left by 2 elements
  %rdx1 = add <4 x i32> %x, %shuf1 ; 0+2 : 1+3 : undef : undef
  %shuf2 = shufflevector <4 x i32> %rdx1, <4 x i32> undef, <4 x i32> <i32 1,
i32 undef, i32 undef, i32 undef> ; shift left 1 element
  %rdx2 = add <4 x i32> %rdx1, %shuf2 ; 0+1+2+3 in first vec elt
  %31 = extractelement <4 x i32> %rdx2, i32 0

This pattern would then be recognized as a canonical reduction. 

I was looking for a similar transform to help bug 23116.

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